FinFET stress engineering using 3D mechanical stress and 2D Monte Carlo device simulation

Abstract

A simulation methodology for FinFET stress and crystallographic orientation engineering is introduced and applied to tall scaled p- and n-type FinFETs with strained nitride layers on (001) wafers. The methodology consists of combining 3D mechanical stress simulation with 2D Monte Carlo device simulation where an averaged channel stress tensor is used. 50 nm down to 10 nm gate-length p- and n-type FinFETs with (110)/110 surface and channel orientation as well as (010)/100 n-type FinFETs are simulated with compressively and tensile strained cap layers, respectively, where liner stress values from 0.8 to 2.0 GPa are considered. Stress-induced Idsat gains in the range of 10 to 35% are found for pFinFETs with increasing tendency upon scaling, while the nFinFETs involve gains between 5 and 15% decreasing for smaller gate lengths with the highest absolute current being obtained for the 100 channel direction.