Impact of Si-thickness on interface and device properties for Si-passivated Ge pMOSFETs

Abstract

The semiconductor-dielectric interface passivation of Ge pMOSFETs with an epitaxially grown Si-layer is studied by means of the full conductance technique. This technique resolves several issues which occur for alternative MOS-interfaces when using the dasiaclassicalpsila conductance technique. The observed mobility behavior as a function of Si-passivation thickness can be explained by the observed variation in interface state density. Observed threshold voltage shifts as a function of Si-passivation thickness can also be linked to the variation in interface state density with thickness.