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Vacancy engineering for highly activated ‘diffusionless’ boron doping in bulk silicon 块状硅中高活性无扩散硼掺杂的空位工程
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681755
N. Bennett, N. Cowern, S. Paul, W. Lerch, H. Kheyrandish, A.J. Smith, R. Gwilliam, B. Sealy
{"title":"Vacancy engineering for highly activated ‘diffusionless’ boron doping in bulk silicon","authors":"N. Bennett, N. Cowern, S. Paul, W. Lerch, H. Kheyrandish, A.J. Smith, R. Gwilliam, B. Sealy","doi":"10.1109/ESSDERC.2008.4681755","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681755","url":null,"abstract":"Simulation and physical experiments have shown that vacancy engineering implants have the potential to provide outstanding pMOS source/drain performance for several future CMOS device generations. Using vacancy-generating implants prior to boron implantation, hole concentrations approaching 1021cm-3 can be achieved using low thermal budget annealing. In this new study we propose that the vacancy engineering technique is not reliant on the implementation of SOI-based CMOS but is also directly applicable to bulk silicon technologies.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128534709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Metal gate thickness optimization for MuGFET performance improvement 金属栅极厚度优化用于MuGFET性能的改善
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681733
I. Ferain, N. Collaert, B. O’Sullivan, T. Conard, M. Popovici, S. Van Elshocht, J. Swerts, M. Jurczak, K. De Meyer
{"title":"Metal gate thickness optimization for MuGFET performance improvement","authors":"I. Ferain, N. Collaert, B. O’Sullivan, T. Conard, M. Popovici, S. Van Elshocht, J. Swerts, M. Jurczak, K. De Meyer","doi":"10.1109/ESSDERC.2008.4681733","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681733","url":null,"abstract":"In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization of MuGFETs and the physical analysis of their gate stacks, we show that the thickness of the TiN metal gate affects the nature of its reaction with the gate dielectric. This, in return, results into threshold voltage (VT) and gate inversion thickness (Tinv) modifications which can explain performance enhancement in n-FETs without any performance loss in p-FETs.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127679286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Revised analysis of the mobility and ION degradation in high-κ gate stacks: Surface optical phonons vs. remote Coulomb scattering 高κ栅极堆叠中迁移率和离子退化的修正分析:表面光学声子与远程库仑散射
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681744
P. Toniutti, P. Palestri, D. Esseni, L. Selmi
{"title":"Revised analysis of the mobility and ION degradation in high-κ gate stacks: Surface optical phonons vs. remote Coulomb scattering","authors":"P. Toniutti, P. Palestri, D. Esseni, L. Selmi","doi":"10.1109/ESSDERC.2008.4681744","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681744","url":null,"abstract":"We use Multi-Subband Monte Carlo simulations to understand which mechanism is mainly responsible for the mobility degradation observed in nMOSFETs featuring high-kappa dielectrics. Direct comparison with the experimental data of Casse et al. [1] points out that for realistic interfacial layer thicknesses the effect of surface optical phonons on the mobility is very modest, and that the measured mobility reduction can be attributed to remote Coulomb scattering of charge in the gate-stack with concentrations in the order of 1014cm-2. We found that the drain current reduction in short channel devices is, instead, not as strong as the mobility reduction.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization 通过源极-漏极植入优化改进全耗尽finfet的翅片宽度缩放
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681766
R. Duffy, M. V. van Dal, B. Pawlak, N. Collaert, L. Witters, R. Rooyackers, M. Kaiser, R. Weemaes, M. Jurczak, R. Lander
{"title":"Improved fin width scaling in fully-depleted FinFETs by source-drain implant optimization","authors":"R. Duffy, M. V. van Dal, B. Pawlak, N. Collaert, L. Witters, R. Rooyackers, M. Kaiser, R. Weemaes, M. Jurczak, R. Lander","doi":"10.1109/ESSDERC.2008.4681766","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681766","url":null,"abstract":"Scaling the fin width in fully-depleted FinFETs can improve short channel effect control, but may be accompanied by a on-state drive current degradation. Ion implantation is a leading candidate as the means to introduce dopants into the silicon, but is often accompanied by amorphization when highly doped source-drain regions are formed. Thin-body silicon recrystallization after amorphization is not as straight-forward as bulk silicon. Crystalline integrity is worse as the fin width is scaled, thereby reducing dopant activation and increasing access resistance. In this work we demonstrate that non-amorphizing implant approaches can overcome drive degradation down to 10 nm wide fins in pMOS FinFETs.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115520346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
On the stability of fully depleted SOI MOSFETs under lithography process variations 光刻工艺变化下全耗尽SOI mosfet的稳定性
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681731
C. Kampen, T. Fuhner, A. Burenkov, A. Erdmann, J. Lorenz, H. Ryssel
{"title":"On the stability of fully depleted SOI MOSFETs under lithography process variations","authors":"C. Kampen, T. Fuhner, A. Burenkov, A. Erdmann, J. Lorenz, H. Ryssel","doi":"10.1109/ESSDERC.2008.4681731","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681731","url":null,"abstract":"In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of MOSFET devices has been evaluated by process and device simulations. FD SOI MOSFETs have been compared to bulk MOSFETs.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127386074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Detection of single-charge polarisation in silicon double quantum dots by using serially-connected multiple single-electron transistors 用串联的多个单电子晶体管检测硅双量子点的单电荷极化
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681763
Y. Kawata, S. Oda, Y. Tsuchiya, Hiroshi Mizuta
{"title":"Detection of single-charge polarisation in silicon double quantum dots by using serially-connected multiple single-electron transistors","authors":"Y. Kawata, S. Oda, Y. Tsuchiya, Hiroshi Mizuta","doi":"10.1109/ESSDERC.2008.4681763","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681763","url":null,"abstract":"We investigate novel serially-connected multiple single-electron transistors (MSETs) as a single-charge polarisation readout for silicon integrated charge qubits. We first design and analyse the double single-electron transistors (DSETs) in which double quantum dots are connected in series with two side gates. We show that the DSETs are sufficiently sensitive to distinguish all the single-charge polarisation states on the two charge qubits integrated adjacently. We also show the scalability of the MSETs by extending our analysis to a scaled-up system of serial triple single-electron transistors (TSETs) integrated with triple charge qubits. Finally we fabricate the DSETs with double charge qubits on the silicon-on-insulator substrate and observe hysteresis in the Coulomb oscillations of the tunnel current at temperature of 4.2 K, which are attributable to the change of polarisation in the double charge qubits.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125254054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of rugged High Voltage high power P-channel silicon MOSFET for plasma applications 用于等离子体应用的高电压高功率p沟道硅MOSFET的设计
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681701
Jinshu Zhang, D. Sdrulla, D. Tsang, D. Frey, G. Krausse
{"title":"Design of rugged High Voltage high power P-channel silicon MOSFET for plasma applications","authors":"Jinshu Zhang, D. Sdrulla, D. Tsang, D. Frey, G. Krausse","doi":"10.1109/ESSDERC.2008.4681701","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681701","url":null,"abstract":"High voltage P-channel RF MOSFET was designed and fabricated by a proprietary self-aligned VDMOS process. When this device is used for class C application at an operating frequency of 40.68 MHz and drain bias of 125 V, the CW output power can reach 350 W, and power gain is 18 dB. Therefore, this 500 V P-channel MOSFET can be used as high side switch transistor in half bridge circuit to generate more RF power for plasma applications up to 40.68 MHz.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121870742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Advantage of La2O3 gate dielectric over HfO2 for direct contact and mobility improvment La2O3栅极电介质在直接接触和提高迁移率方面优于HfO2
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681715
K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai
{"title":"Advantage of La2O3 gate dielectric over HfO2 for direct contact and mobility improvment","authors":"K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai","doi":"10.1109/ESSDERC.2008.4681715","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681715","url":null,"abstract":"Advantage of La<sub>2</sub>O<sub>3</sub> over HfO<sub>2</sub> MOSFET has been experimentally examined. Silicate reaction especially observed at La<sub>2</sub>O<sub>3</sub>/Si interface has been found to suppress the formation of SiO<sub>2</sub> layer to realize direct contact, which is useful for further scaling in equivalent oxide thickness (EOT). Due to the lack of interfacial layer, La<sub>2</sub>O<sub>3</sub> has showed relatively high interfacial state density, however, the effective mobility has exceeded to that of HfO<sub>2</sub> MOSFET. Mobility analysis has revealed an additional Coulomb scattering at small EOT, suggesting the influence of metal gate. A simple mobility degradation model is pointed out using metal induced defects.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130676745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Ge p-channel MOSFETS with La2O3 and Al2O3 gate dielectrics 采用La2O3和Al2O3栅极介质的Ge p沟道mosfet
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681703
C. Rossel, A. Dimoulas, A. Tapponnier, D. Caimi, D. Webb, C. Andersson, M. Sousa, C. Marchiori, H. Siegwart, J. Fompeyrine, R. Germann
{"title":"Ge p-channel MOSFETS with La2O3 and Al2O3 gate dielectrics","authors":"C. Rossel, A. Dimoulas, A. Tapponnier, D. Caimi, D. Webb, C. Andersson, M. Sousa, C. Marchiori, H. Siegwart, J. Fompeyrine, R. Germann","doi":"10.1109/ESSDERC.2008.4681703","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681703","url":null,"abstract":"We report on p-MOSFETs based on La<sub>2</sub>O<sub>3</sub>, Al<sub>2</sub>O<sub>3</sub> and a mixture of both as high-k dielectric deposited by molecular beam epitaxy (MBE). Mobilities of about 140 cm<sup>2</sup>/Vs were achieved, which are 1.3 to 1.5 times larger than the universal hole mobility of Si/SiO<sub>2</sub>. This demonstrates the potential advantage of La<sub>2</sub>O<sub>3</sub>-based Ge p-MOSFETs over Si devices. The negative threshold voltages V<sub>T</sub>, which range between -0.2 and -1 V, make these gate stacks particularly attractive, given the fact that in several cases Ge p-MOSFETs exhibit an unwanted positive V<sub>T</sub> shift.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Study on aggressive proximity of embedded SiGe with comprehensive SDE engineering for 32 nm-node high-performance pMOSFET technology 基于32纳米节点高性能pMOSFET技术综合SDE工程的嵌入式SiGe侵略性接近研究
ESSDERC 2008 - 38th European Solid-State Device Research Conference Pub Date : 2008-11-18 DOI: 10.1109/ESSDERC.2008.4681764
H. Okamoto, N. Yasutake, N. Kusunoki, K. Adachi, H. Itokawa, K. Miyano, T. Ishida, A. Hokazono, S. Kawanaka, I. Mizushima, A. Azuma, Y. Toyoshima
{"title":"A Study on aggressive proximity of embedded SiGe with comprehensive SDE engineering for 32 nm-node high-performance pMOSFET technology","authors":"H. Okamoto, N. Yasutake, N. Kusunoki, K. Adachi, H. Itokawa, K. Miyano, T. Ishida, A. Hokazono, S. Kawanaka, I. Mizushima, A. Azuma, Y. Toyoshima","doi":"10.1109/ESSDERC.2008.4681764","DOIUrl":"https://doi.org/10.1109/ESSDERC.2008.4681764","url":null,"abstract":"We have presented the high performance pMOSFET with embedded SiGe (eSiGe) technique which is applicable to 32 nm node ground rule (dense gate space). In general, close eSiGe S/D structure to the channel improves pMOSFET performance because of higher strain in the channel. However, we found the relation between boron diffusion modulation in SiGe region and short channel effect (SCE) in the context of eSiGe proximity change. Therefore, additional source drain extension (SDE) optimization is required to improve device performance with close eSiGe structure focusing on parasitic resistance reduction. As a results, we have demonstrated high drive current of 755 muA/mum at Vdd = 1.0 V, IOFF = 100 nA/mum, 30 nm gate length pMOSFET.","PeriodicalId":121088,"journal":{"name":"ESSDERC 2008 - 38th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133923659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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