1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)最新文献_第2页

The effects of preparation conditions of SIMOX samples on the photoluminescence spectra of their buried oxide layer 研究了SIMOX样品制备条件对其埋藏氧化层光致发光光谱的影响

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819885

W. Skorupa, L. Rebohle, A. Revesz, H. Hughes

引用次数: 0

The off leakage in SOI-MOS transistors and the impact on the standby current of ULSI's SOI-MOS晶体管的漏关及其对ULSI待机电流的影响

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819845

A. Adan, K. Higashi, K. Nimi, T. Ashida

引用次数: 2

MEMS for space applications MEMS用于空间应用

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819857

T. Tang

{"title":"MEMS for space applications","authors":"T. Tang","doi":"10.1109/SOI.1999.819857","DOIUrl":"https://doi.org/10.1109/SOI.1999.819857","url":null,"abstract":"Summary form only given. At NASA, the focus for smaller, less costly missions has encouraged the development of microspacecraft. MEMS technology advances in terms of sensors, propulsion systems, and instruments make the notion of a specialized microspacecraft feasible in the immediate future. Emerging MEMS technology offers the integration of recent advances in micromachining and nanofabrication techniques with microelectronics in a mass-producible format, and is viewed as the next step in device and instrument miniaturization. MEMS technology has the potential to enable or enhance NASA missions in numerous ways. The technology allows component and system miniaturization, where the primary benefit is reduction in size, mass and power. MEMS technology also provides new capabilities and enhanced performance, with the greatest impact in performance, regardless of system size. Finally, with the availability of mass-produced, miniature MEMS instrumentation comes the opportunity to rethink fundamental measurement paradigms. It is now possible to expand horizons from a single instrument perspective to one involving multi-node or distributed systems. Distributed systems and missions give a new system in which functionality is enabled by a multiplicity of elements. In the future, integration of electronics, photonics, and micromechanical functionalities into \"instruments-on-a-chip\" will provide the ultimate size, cost, function and performance advantages. This presentation discusses recent developments and applications of MEMS technologies and devices for space applications.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127256713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Electrostatic discharge protection in silicon-on-insulator technology 绝缘体上硅技术中的静电放电保护

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819858

S. Voldman, D. Hui, L. Warriner, D. Young, R. Williams, J. Howard, V. Gross, W. Rausch, E. Leobangdung, M. Sherony, N. Rohrer, C. Akrout, F. Assaderaghi, G. Shahidi

{"title":"Electrostatic discharge protection in silicon-on-insulator technology","authors":"S. Voldman, D. Hui, L. Warriner, D. Young, R. Williams, J. Howard, V. Gross, W. Rausch, E. Leobangdung, M. Sherony, N. Rohrer, C. Akrout, F. Assaderaghi, G. Shahidi","doi":"10.1109/SOI.1999.819858","DOIUrl":"https://doi.org/10.1109/SOI.1999.819858","url":null,"abstract":"Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) semiconductor technology is perceived as a major roadblock for the SOI technology to become a viable mainstream contender for high-performance advanced CMOS semiconductor chips (Hu, 1994; Colinge, 1991). In this paper, our results in four successive SOI technology generations demonstrate that excellent ESD protection levels are achievable in SOI chips with no additional masking steps, process implants, costs or ESD design area. ESD results also show that the ESD robustness of the SOI ESD device is improving with partially depleted SOI MOSFET scaling from 0.25 to 0.12 /spl mu/m L/sub eff/ technology generations (Shahidi et al., 1999; Voldman et al., 1995, 1997, 1999). By allowing the ESD network minimum design to scale with the technology, improved ESD results are evident in each generation with no indication of any SOI-specific ESD limitations. For future technology generations below 1.5 V V/sub DD/ power supply, continued improvement is anticipated due to buried-oxide scaling, lower trigger voltages, dynamic threshold voltage MOSFET (DTMOS) techniques and ESD I/O design learning (Voldman et al, 1997; Assaderaghi et al., 1994). ESD protection of partially depleted SOI technology is not a problem or technology concern using our proposed ESD methodology.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128779989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Detailed analysis of the gate delay variability in partially depleted SOI CMOS circuits 部分耗尽SOI CMOS电路中栅极延迟变异性的详细分析

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819848

I. Aller, K. Kroell

引用次数: 9

Temperature dependence of AC floating body effects in PD SOI nMOS PD SOI nMOS中交流浮体效应的温度依赖性

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819841

Y. Tseng, W.M. Huang, C. Hwang, P. Welch, J. Woo

引用次数: 5

Single chip wireless systems using SOI 使用SOI的单芯片无线系统

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819833

R. Reedy, J. Cable, D. Kelly

引用次数: 14

Mechanisms of dynamic pass leakage current in partially depleted SOI MOSFETs 部分耗尽SOI mosfet中动态通漏电流的机理

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819864

T. Saraya, T. Hiramoto

引用次数: 1

Advanced Microelectronics: the role of SOI 先进微电子:SOI的作用

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819832

D. Radack

引用次数: 6

Novel 3-D structures [ICs] 新型三维结构

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819855

K. Saraswat, S. Souri, V. Subramanian, A. Joshi, A.W. Wang

{"title":"Novel 3-D structures [ICs]","authors":"K. Saraswat, S. Souri, V. Subramanian, A. Joshi, A.W. Wang","doi":"10.1109/SOI.1999.819855","DOIUrl":"https://doi.org/10.1109/SOI.1999.819855","url":null,"abstract":"Summary form only given. Interconnect delays are increasingly dominating IC performance due to increased chip size and reductions in minimum feature size. Despite new materials like Cu with low-k dielectrics, interconnect delay is expected to be substantial below the 130 nm technology node, severely limiting chip performance. The need therefore exists for alternative technologies to overcome this problem. One such promising technique is 3D ICs with multiple active Si layers. In a 3D structure, a large number of information signal paths could be transferred from horizontal to vertical interconnects. 3D device integration in multiple Si layers obtainable via technologies like crystallization of amorphous Si and wafer bonding can potentially reduce chip area by increasing transistor packing density and reducing wiring requirements for wire-pitch limited ICs. Recently, we have estimated chip area for 3D ICs and demonstrated significant reductions in interconnect delay for a 0.18 /spl mu/m technology chip with 8 million gates (Souri et al., 1999). In this work, we generalize this analysis using NTRS technology projections down to the 50 nm node. The performance analysis incorporates the effects of increasing the number of active layers, moving repeaters from the substrate to upper active layers and optimizing wiring networks. Interconnect delay as a function of technology is calculated using data projected by the NTRS for 2D ICs. Also shown are delays for 3D ICs with 2 active layers, where wire pitches are increased to match the 2D IC areas, calculated using the 3D chip area estimation model. Interconnect delay is reduced by 64%.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133676143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30