The off leakage in SOI-MOS transistors and the impact on the standby current of ULSI's

Abstract

Summary form only given. The application of SOI-CMOS to low-voltage, battery-powered devices is facing the practical trade-off between low threshold voltage and off-state leakage current. For typical portable electronic equipment, the specification for standby power dissipation restricts the MOSFET off-current to I/sub doff/<10 pA//spl mu/m, which should be compared with I/sub doff//spl sim/1 nA//spl mu/m in high-speed microprocessors (Leonbandung et al., 1998). In this paper, we investigate the off-current mechanism in SOI MOSFETs and its relationship with the IC's standby current for quantitative modeling. The model parameter extraction techniques are also described.