1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)最新文献

A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique 一种新颖的0.7 V双端口6T SRAM存储单元结构，采用部分耗尽SOI CMOS动态阈值技术，具有单比特线同时读写访问(SBLSRWA)能力

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-27 DOI: 10.1109/SOI.1999.819860

S. Liu, J. Kuo

引用次数: 2

An SOI nano flash memory device 一种SOI纳米闪存器件

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819872

Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge

引用次数: 0

Defect analysis of patterned SOI material 图案化SOI材料缺陷分析

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819882

S. Bagchi, Y. Yu, M. Mendicino, J. Conner, A. Anderson, L. Prabhu, M. Tiner, M. Alles

{"title":"Defect analysis of patterned SOI material","authors":"S. Bagchi, Y. Yu, M. Mendicino, J. Conner, A. Anderson, L. Prabhu, M. Tiner, M. Alles","doi":"10.1109/SOI.1999.819882","DOIUrl":"https://doi.org/10.1109/SOI.1999.819882","url":null,"abstract":"SOI technology has several advantages over bulk Si, including potentially lower leakage, higher speed, freedom from latch-up, and lowered parasitic capacitance. However, issues such as floating body effects, poorer thermal conductivity, lack of device libraries, etc., can complicate operation, processing, and design of certain devices fabricated on SOI wafers. In such a situation, it may be desirable to have those parts of the circuits that can take advantage of SOI fabricated separately from the other circuits on bulk Si. The traditional approach is a multichip module (MCM), with sub-units fabricated on the appropriate substrate. This can add considerably to the cost and complexity of the final product. An elegant alternative approach is a patterned SOI wafer. Such a wafer has bulk Si areas interspersed with SOI areas, or \"pads\", of desired dimensions. Several technologies have been proposed for fabrication of such wafers (Van Bentum and Vogt, 1998). Perhaps the most promising of them is patterned SIMOX. SIMOX has emerged as a mature processing technology for the production of SOI wafers. Prior to design of device layouts, it is important to take into consideration the type, density, and location of crystalline defects which might be present in the region of transition from bulk Si to the SOI pads. In this paper, we report the results of our investigation of crystalline defects in patterned SIMOX wafers.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evidence of energetically-localized trap-states at SOI-BOX interface in high-dose SIMOX wafers 高剂量SIMOX晶圆中SOI-BOX界面能量局域阱态的证据

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819852

T. Ushiki, K. Kotani, T. Funaki, K. Kawai, T. Ohmi

引用次数: 1

Thermal modeling of thin-film SOI transistors 薄膜SOI晶体管的热建模

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819842

M. Asheghi, P. Sverdrup, K. Goodson

引用次数: 7

Performance trade-offs of argon implanted SOI MOSFETs with In and Sb retrograde channel doping In和Sb逆行通道掺杂下氩注入SOI mosfet的性能权衡

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819867

X.-L. Xu, R. Widenhofer, Y. Yu, O. Zia, S. Pozder, D. Hall, M. Rashed, D. Chang, S. Jallepalli, D. Connelly, T. Van Gompel, M. Olivares, M. Mendicino, J. Candelaria, S. Veeraraghavan, D. Dow

引用次数: 1

A 1.8 V 2.5 GHz PLL using 0.18 /spl mu/m SOI/CMOS technology 采用0.18 /spl mu/m SOI/CMOS技术的1.8 V 2.5 GHz锁相环

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819834

K. Yoshimura, K. Ueda, T. Nakura, K. Kubo, K. Mashiko, S. Maeda, S. Maegawa, Y. Yamaguchi, Y. Matsuda

{"title":"A 1.8 V 2.5 GHz PLL using 0.18 /spl mu/m SOI/CMOS technology","authors":"K. Yoshimura, K. Ueda, T. Nakura, K. Kubo, K. Mashiko, S. Maeda, S. Maegawa, Y. Yamaguchi, Y. Matsuda","doi":"10.1109/SOI.1999.819834","DOIUrl":"https://doi.org/10.1109/SOI.1999.819834","url":null,"abstract":"Summary form only given. This paper shows a 2.5 GHz PLL circuit for high-speed communication devices using a 0.18 /spl mu/m SOI/CMOS technology. The technology uses a shallow trench structure to effectively isolate active devices on a thin film SOI substrate. We employed floating-body SOI/CMOS in this chip. We applied a ring oscillator for the voltage controlled-oscillator (VCO). The well-known issues of SOI do not affect the circuit stability and noise performance of our PLL circuit for several reasons. Firstly, as the frequency range required for the VCO is comparatively narrow, the floating-body configuration would have little effect on circuit operation (Ueda et al., 1996). Secondly, thermal equilibrium on the ring oscillator can be achieved within a few microseconds (Tenbroek et al., 1998). Then the self-heating issue would be insignificant for the lock-in process of the PLL. Besides this, the buried oxide of SOI and shallow trench isolation reduces the crosstalk noise from the large digital logic block which is the most potentially serious problem for system-level integration of sensitive circuits and large logic blocks.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128666192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fractional implantation area effects on patterned ion-cut silicon layer transfer 分数注入面积对图案离子切割硅层转移的影响

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819886

C. Yun, N. Cheung

引用次数: 0

A body-contact SOI MOSFET model for circuit simulation 用于电路仿真的体接触SOI MOSFET模型

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819853

P. Su, S. Fung, F. Assaderaghi, C. Hu

引用次数: 7

Temperature dependent hysteretic propagation delay in FB SOI inverter chain fbsoi逆变器链中温度相关的滞回传播延迟

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819863

D. Chang, Byonug Min, S. Veeraraghavan, M. Mendicino, T. Cooper, S. Egley, K. Cox

{"title":"Temperature dependent hysteretic propagation delay in FB SOI inverter chain","authors":"D. Chang, Byonug Min, S. Veeraraghavan, M. Mendicino, T. Cooper, S. Egley, K. Cox","doi":"10.1109/SOI.1999.819863","DOIUrl":"https://doi.org/10.1109/SOI.1999.819863","url":null,"abstract":"The CMOS gate delay on SOI depends on the switching history of floating-body transistors, which introduces uncertainty in predicting the performance of SOI-based circuits (Suh and Fossum, 1994; Shahidi et al., 1999). The main cause of the hysteretic delay is due to the transient variation of the body voltage during switching and the corresponding threshold voltage change. Since the capacitance coupling and generation/recombination currents determining the transient body-voltage are strong functions of temperature, the gate delay is also expected to show a significant temperature dependence. In the measurement of a 610-stage floating-body SOI CMOS open-ended inverter chain, we have observed that the hysteretic gate delay variation is worse at higher temperature for devices which showed pulse compression at room temperature. In this work, we have performed simulations to predict fast/slow gate delays for different SOI device structures versus temperature, and compared these results to measurements, thus illustrating the importance of accounting for temperature in history effects.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4