Temperature dependent hysteretic propagation delay in FB SOI inverter chain

Abstract

The CMOS gate delay on SOI depends on the switching history of floating-body transistors, which introduces uncertainty in predicting the performance of SOI-based circuits (Suh and Fossum, 1994; Shahidi et al., 1999). The main cause of the hysteretic delay is due to the transient variation of the body voltage during switching and the corresponding threshold voltage change. Since the capacitance coupling and generation/recombination currents determining the transient body-voltage are strong functions of temperature, the gate delay is also expected to show a significant temperature dependence. In the measurement of a 610-stage floating-body SOI CMOS open-ended inverter chain, we have observed that the hysteretic gate delay variation is worse at higher temperature for devices which showed pulse compression at room temperature. In this work, we have performed simulations to predict fast/slow gate delays for different SOI device structures versus temperature, and compared these results to measurements, thus illustrating the importance of accounting for temperature in history effects.