1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)最新文献_第6页

Optimal double-gate MOSFETs: symmetrical or asymmetrical gates? 最佳双栅极mosfet:对称还是不对称栅极?

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819871

Keunwoo Kim, J. Fossum

{"title":"Optimal double-gate MOSFETs: symmetrical or asymmetrical gates?","authors":"Keunwoo Kim, J. Fossum","doi":"10.1109/SOI.1999.819871","DOIUrl":"https://doi.org/10.1109/SOI.1999.819871","url":null,"abstract":"Due to their near-ideal intrinsic features, double-gate (DG) MOSFETs (with thin, fully depleted (FD) Si-film (SOI) bodies) are of interest for possible future CMOS IC applications with L/sub eff/ approaching the lateral scaling limit (/spl sim/20 nm) (Fossum and Chong, 1998; Wong et al. 1998). Much of this interest stems from the two-channel property of the symmetrical-gate DG device and the implied higher current drive. More important, we believe, is the electrical coupling of the two gates through the FD Si film. This coupling underlies the inherent suppression of SCEs and the excellent subthreshold slope, which translate to high I/sub on//I/sub off/ ratios. In fact, as we show in this paper, the coupling can be exploited more in asymmetrical-gate DG MOSFETs (Fossum and Chong, 1998; Tanaka et al. 1994) than in symmetrical ones. We rely on numerical device simulations, using MEDICI and its hydrodynamic-transport option, and SOISPICE circuit simulations, using the UFSOI/FD MOSFET model (Fossum et al. 1998), to convey insight regarding performance and optimal design of DG MOSFETs and to reveal the inherent superiority of asymmetrical gates.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130463550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Advances in silicon-on-insulator photonic integrated circuit (SOIPIC) technology 绝缘体上硅光子集成电路技术的研究进展

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819856

M. Naydenkov, B. Jalali

引用次数: 12

SIMOX SOI surface smoothing for gate oxide integrity and reliability SIMOX SOI表面平滑栅极氧化物的完整性和可靠性

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819880

L. Allen, D. Fenner, W. Skinner, R. Chandonnet, S.E. Deziel, R. Torti, N. Toyoda

引用次数: 0

Effect of single-step, high-oxygen-concentration annealing on buried oxide layer microstructure in post-implant-amorphized, low-dose SIMOX material 单步高氧退火对低剂量SIMOX材料植入后非晶化埋地氧化层微观结构的影响

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI: 10.1109/SOI.1999.819883

L. Chen, S. Bagchi, S. Krause, P. Roitman

{"title":"Effect of single-step, high-oxygen-concentration annealing on buried oxide layer microstructure in post-implant-amorphized, low-dose SIMOX material","authors":"L. Chen, S. Bagchi, S. Krause, P. Roitman","doi":"10.1109/SOI.1999.819883","DOIUrl":"https://doi.org/10.1109/SOI.1999.819883","url":null,"abstract":"Fabrication of high-dose SIMOX (typically 1.8/spl times/10/sup 18/ cm/sup 2/ at 200 keV) is a maturing materials technology with increasing commercial usage. However, lower-dose SIMOX (2 to 4/spl times/10/sup 17/ cm/sup 2/) has the potential to be more economical, as well as allow device designers a choice of oxide thickness, but film uniformity and quality must be as good or better than standard high-dose material. A variety of approaches to produce low-dose SIMOX have been used which include: low dose implant plus ITOX (internal thermal oxidation), which uses a second high temperature anneal with high oxygen concentration (Nakashima et al. 1996; Mrstik et al. 1995); multiple energy implants (Alles, 1997); lower energy implantation (Anc et al. 1998); rapid ramping to the high temperature anneal range (Ogura, 1998); N pre-implantation (Meyappan et al. 1995); and very-low dose, post-implant amorphization prior to high temperature annealing (Holland et al. 1996; Bagchi et al. 1997). For the last technique, it was reported there were changes in the precipitation mechanisms that control BOX development. The first was elimination of multiply-faulted defects as sites for preferred nucleation and growth of oxides which form a discontinuous upper layer of precipitates in untreated material. The second was enhanced diffusion of oxygen along defects and phase boundaries in the amorphized region to the single BOX layer that was developing. In this research, we extend the work on post-implant-amorphized low-dose SIMOX by reporting effects of a single-step high oxygen concentration anneal on its BOX microstructure.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121169178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 /spl mu/m SOI technology 在1.8 V, 0.25 /spl mu/m SOI技术下高性能动态寄存器文件的频率依赖行为

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI: 10.1109/SOI.1999.819862

R. Joshi, W. Hwang, S.C. Wilson, G. Shahidi, C. Chuang

引用次数: 0

Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors 阈值电压设计在部分耗尽SOI和大块CMOS晶体管之间不兼容

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI: 10.1109/SOI.1999.819844

H. van Meer, J. Lyu, S. Kubicek, L. Geenen, K. De Meyer

{"title":"Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors","authors":"H. van Meer, J. Lyu, S. Kubicek, L. Geenen, K. De Meyer","doi":"10.1109/SOI.1999.819844","DOIUrl":"https://doi.org/10.1109/SOI.1999.819844","url":null,"abstract":"Summary form only given. Silicon-on-insulator (SOI) CMOS technology has proven to be compatible with bulk CMOS in many ways, ranging from circuit design and layout to wafer processing. In addition, partially-depleted (PD) SOI technology has been suggested as a method for achieving a high circuit performance at low supply voltage and low power (Jacobs et al, 1998). Unlike fully-depleted (FD) SOI transistors, PD SOI devices have the advantage of a threshold voltage V/sub T/ which is insensitive to variations in the silicon thickness uniformity. Based on device physics, the long-channel threshold voltage V/sub T/ is equal to the V/sub T/ of the bulk transistor as long as the channel doping concentrations are equal. Therefore, PD SOI CMOS design appears to be very similar to conventional bulk. Often, the design of a PD SOI CMOS technology is started from a present and well-known baseline bulk CMOS technology. During device fabrication, it is assumed, however, that the diffusivity of the channel dopants in the vertical direction in SOI is similar to bulk, which is fundamentally incorrect. In order to investigate the threshold voltage difference between PD SOI and bulk, SOI CMOS transistors have been fabricated on BESOI wafers with buried oxide and silicon layer thicknesses of 350 and 125 nm, respectively. In order to obtain a straight comparison with the bulk CMOS technology, each SOI wafer has a bulk counterpart for which the process conditions have been exactly the same.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mainstreaming of the SOI technology SOI技术主流化

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI: 10.1109/SOI.1999.819828

Ghavam G. Shahidi, A. Ajmera, Fariborz Assaderaghi, R. Bolam, Andres Bryant, M. Coffey, H. Hovel, J. Lasky, E. Leobandung, H.-S. Lo, M. Maloney, D. Moy, Werner A. Rausch, D. Sadana, Dominic J. Schepis, M. Sherony, J. Sleight, Lawrence F. Wagner, K. Wu, Bijan Davari, T. Chen

引用次数: 14

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI) 采用本体固定部分沟槽隔离(PTI)的批量布局兼容0.18 /spl mu/m SOI-CMOS技术

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI: 10.1109/SOI.1999.819887

Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura

{"title":"Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)","authors":"Y. Hirano, S. Maeda, T. Matsumoto, K. Nii, T. Iwamatsu, Y. Yamaguchi, T. Ipposhi, H. Kawashima, S. Maegawa, M. Inuishi, T. Nishimura","doi":"10.1109/SOI.1999.819887","DOIUrl":"https://doi.org/10.1109/SOI.1999.819887","url":null,"abstract":"Transistor performance improvement has been strongly required for work toward highly integrated intelligent system LSIs. To meet this demand, silicon on insulator (SOI) has become of major interest for next generation devices, because it can offer durable device scaling as compared with bulk devices (Schepis et al. 1997). The critical issues for SOI are floating-body effects such as deterioration in drain current (Matsumoto et al. 1999), dynamic threshold voltage instability (Lu et al. 1997), and increased soft error rate (Wada et al. 1998). These have restricted the application of floating SOI, especially to analog circuits. Some circuit modifications and body contact insertions are necessary. A full body-fixing structure is another approach and some techniques have been proposed (Koh et al. 1997; Iwamatsu et al. 1995). However, when using these techniques, there have been some shortcomings in terms of scalability and layout compatibility. In this report, we propose a partial trench isolation (PTI) technique in which the body potential is fixed through the region under the trench oxide. With the PTI technology, we can eliminate floating-body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification. Moreover, the feasibility for ULSIs is demonstrated by a fully functional 4 Mbit SRAM.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"470 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123384601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A low power /spl Sigma//spl Delta/ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 /spl mu/m SOI CMOS technology 采用0.25 /spl mu/m SOI CMOS技术，具有50 MHz采样率的低功耗/spl Sigma//spl Delta/模数调制器

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1900-01-01 DOI: 10.1109/SOI.1999.819835

A. Swaminathan, N. Fong, P. Lauzon, Hong-Kui Yang, M. Maliepaard, C. Plett, M. Snelgrove

引用次数: 0