1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)最新文献_第5页

'Self-body-biased' SOI MOSFET through 'depletion isolation effect' 基于“耗尽隔离效应”的“自我偏置”SOI MOSFET

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819846

M. Terauchi, K. Terada

引用次数: 1

A bandgap circuit operating up to 300/spl deg/C using lateral bipolar transistors in thin-film CMOS-SOI technology 采用薄膜CMOS-SOI技术的横向双极晶体管，工作温度高达300/spl度/C的带隙电路

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819838

S. Adriaensen, V. Dessard, D. Flandre

引用次数: 21

An SOI single-electron transistor SOI单电子晶体管

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819851

Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge

引用次数: 6

SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing 金属诱导横向结晶(MILC)和高温退火法制备非晶硅SOI

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819878

S. Jagar, M. Chan, K. C. Poon, Hongmei Wang, M. Qin, S. Shivani, P. Ko, Yangyuan Wang

{"title":"SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing","authors":"S. Jagar, M. Chan, K. C. Poon, Hongmei Wang, M. Qin, S. Shivani, P. Ko, Yangyuan Wang","doi":"10.1109/SOI.1999.819878","DOIUrl":"https://doi.org/10.1109/SOI.1999.819878","url":null,"abstract":"In current SOI technology, the formation of circuit elements requires the use of some special starting material like SIMOX, BESOI or Unibond wafers, which usually cannot be made in-house. As such, it leads to a divergence between SOI technology and bulk technology, and there are debates on justification on the initial material cost. TFTs formed in polysilicon have similar structures to SOI, and have been used as the load element in SRAM. Comparing TFT and SOI transistors, the TFT is easier to fabricate in term of starting material and compatibility with bulk processes. However, its performance is usually very poor for high performance circuits. The TFT structure consists of a large number of small size crystallized silicon grains. It is desirable to have a very large grain size so that a single transistor can lie entirely on a single grain. In this case, the TFT becomes an SOI MOSFET. Metal-induced-lateral-crystallization (MILC) has been used to enlarge the polysilicon TFT grain size. However, due to the limitation in low temperature formation, the grain size is still not desirable. With the use of high temperature annealing at a temperature above 900/spl deg/C after MILC, we found that much larger crystals of the order of 10 /spl mu/m can be formed. For the advanced technology which comes with device scaling, it is possible to individually recrystallize the active region of each transistor, giving TFTs (as formed) with SOI MOSFET performance.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117170674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

High frequency characterization of SOI dynamic threshold voltage MOS (DTMOS) transistors SOI动态阈值电压MOS晶体管的高频特性

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819840

V. Ferlet-Cavrois, A. Bracale, N. Fel, O. Musseau, C. Raynaud, O. Faynot, J. Pelloie

引用次数: 9

IOS-a new type of materials combination for system-on-a chip preparation 一种新型的片上系统制备材料组合

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819874

Q. Tong, L. Huang, Y. Chao, Q. Gang, U. Goesele

{"title":"IOS-a new type of materials combination for system-on-a chip preparation","authors":"Q. Tong, L. Huang, Y. Chao, Q. Gang, U. Goesele","doi":"10.1109/SOI.1999.819874","DOIUrl":"https://doi.org/10.1109/SOI.1999.819874","url":null,"abstract":"IOS (insulator-on-semiconductor) has emerged as a new type of materials combination for system-on-a chip preparation. For high frequency mobile communication systems, a thin layer of piezoelectric or ferroelectric oxide crystal such as quartz, LiTaO/sub 3/ or LiNbO/sub 3/ on Si is required for high Q-factor and low temperature coefficient SAW filters, surface resonators and oscillators. Combining these materials with Si can lead to the integration of electronic and acoustic devices on the same chip. Voltage-controlled and temperature-compensated high Q-factor crystal oscillators and resonators can thus be realized. The integration of high performance GaAs photodetectors with LiNbO/sub 3/ waveguides makes integrated optical circuits possible. By preparing a thin layer of single crystalline transition metal oxides such as magnetic garnets on Si or on III-V semiconductors, stabilized laser diodes can be realized due to the availability of on-chip thin film optical isolators and circulators. Layer transfer by wafer bonding and H-induced layer splitting provides a manufacturable technology for IOS preparation. In this study, we report feasibility study results for IOS preparation with an insulator layer of many single crystalline insulators such as c-sapphire, LaAlO/sub 2/, PLZT and LiNbO/sub 3/. We have demonstrated that surface blistering and layer splitting of these materials is possible if H implantation is performed at wafer temperatures within the specific temperature range for each material.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126560686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

1.5-V 1.8-GHz SOI low noise amplifiers for PCS receivers 用于PCS接收机的1.5 v 1.8 ghz SOI低噪声放大器

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819836

W. Jin, Philip C. H. Chan, C. Hai

引用次数: 5

Multi-layer SOI island technology by selective epitaxial growth for single-gate and double-gate MOSFETs 单门和双门mosfet的选择性外延生长多层SOI岛技术

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819876

S. Pae, J. Denton, G. Neudeck

{"title":"Multi-layer SOI island technology by selective epitaxial growth for single-gate and double-gate MOSFETs","authors":"S. Pae, J. Denton, G. Neudeck","doi":"10.1109/SOI.1999.819876","DOIUrl":"https://doi.org/10.1109/SOI.1999.819876","url":null,"abstract":"Continued device scaling in bulk MOSFETs beyond the sub-100 nm regime may require transition to advanced SOI technologies. It has been reported that the thin film fully-depleted (FD) SOI structure is promising for low voltage, high speed applications due to the improved short channel tolerance and lack of body effect (Wong et al, 1998). However, current techniques to obtain bulk-like quality material for very thin SOI have proved difficult to manufacture in terms of cost, material defects and SOI thickness variation across the wafer. The SOI thickness variation results in V/sub T/ variation, which is a major drawback in FD-SOI technology. Selective epitaxial growth (SEG) offers an alternative way of obtaining a device quality SOI material when it is grown laterally (epitaxial lateral overgrowth; ELO) over the field SiO/sub 2/. The local area chemical mechanical polishing (CMP) etch stop gives good controlled thickness of uniform thin SOI films where FD-SOI MOSFETs can be fabricated (Pae et al, 1998 and 1999). One distinctive advantage of the ELO technique is the formation of very thin bottom gate SiO/sub 2/ for double gate MOSFETs (Wong et al. 1997; Denton et al. 1995), which is difficult to obtain in other SOI technologies. This enables improved dynamic V/sub T/ control using low back gate bias. We report here the most recent results of deep-submicron FD-SOI P-MOSFETs fabricated in two different layers of SOI islands created entirely by ELO. Device characteristics and dynamic V/sub T/ shifting are discussed.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134104838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Advanced silicide for sub-0.18 /spl mu/m CMOS on ultra-thin (35 /spl mu/m) SOI 在超薄(35 /spl mu/m) SOI上用于低于0.18 /spl mu/m CMOS的先进硅化物

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819866

L. Ren, B. Cheng, J. Woo

{"title":"Advanced silicide for sub-0.18 /spl mu/m CMOS on ultra-thin (35 /spl mu/m) SOI","authors":"L. Ren, B. Cheng, J. Woo","doi":"10.1109/SOI.1999.819866","DOIUrl":"https://doi.org/10.1109/SOI.1999.819866","url":null,"abstract":"As CMOS device dimensions are scaled toward 0.1 /spl mu/m, formation of controllable thin silicide is critical. For conventional high temperature Ti salicidation, however, it is difficult to control silicide formation due to a fast reaction rate between Ti metal and silicon. Co silicide can achieve low sheet resistance for fine polysilicon lines and source/drain (S/D) regions, but the diode leakage is still a major problem with shallower junctions and SOI for deep sub-micron CMOS (Hsiao et al., 1998). In the past, a low temperature silicide technology has been proposed and applied to 100-nm SOI MOSFETs (Goto et al., 1995). In this paper, Ge/sup +/ pre-amorphized Ti salicide for sub-0.1 /spl mu/m gate length CMOS is investigated in detail and is used to demonstrate 0.1 /spl mu/m CMOS on an ultra thin SOI film of 35 nm for the first time. We focused on the influence of Ge/sup +/ pre-amorphization energy, Ti metal thickness and substrate doping on Ti silicidation kinetics, silicide depth and sheet resistance on bulk and fine polysilicon lines ranging from 1.0 to 0.1 /spl mu/m. Our results showed an effective control of silicide depth in the case of Ge/sup +/-implanted samples. A small grain size averaging 80 nm was observed on fine gate lines and polysilicon lines down to 0.1 m were shown to have good resistivity. The effects of metal thickness and doping species were eliminated. The excellent device performance shows this technology is highly suitable for future 0.1 /spl mu/m SOI MOSFETs and deep sub-micron bulk CMOS devices.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Integrity of the gate oxide on the thin top Si layer in ITOX-SIMOX wafers ITOX-SIMOX晶圆上硅薄层栅极氧化物的完整性

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819881

S. Nakashima, J. Kodate

引用次数: 1