1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)最新文献_第4页

SOI MOSFET fluctuation limits on gigascale integration (GSI) 千兆级集成(GSI)的SOI MOSFET波动极限

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819849

Xinghai Tang, V. De, Lihui Wang, J. Meindl

引用次数: 5

ELTRAN/sup (R)/ by water-jet splitting in stress-controlled porous Si 应力控制多孔硅中水射流劈裂ELTRAN/sup (R)/

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819877

K. Sakaguchi, K. Yanagita, H. Kurisu, H. Suzuki, K. Ohmi, T. Yonehara

引用次数: 4

Building hybrid active pixels for CMOS imager on SOI substrate 在SOI衬底上构建CMOS成像仪的混合有源像素

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819873

Weiquan Zhang, M. Chan, Hongmei Wang, P. K. Ko

{"title":"Building hybrid active pixels for CMOS imager on SOI substrate","authors":"Weiquan Zhang, M. Chan, Hongmei Wang, P. K. Ko","doi":"10.1109/SOI.1999.819873","DOIUrl":"https://doi.org/10.1109/SOI.1999.819873","url":null,"abstract":"CMOS active pixel sensors (APS) use the advantages of mature CMOS manufacturing technology and are competing with the currently dominant CCD technology in the state-of-the-art imaging applications that require low power, high integration and complex functionality. SOI technology has been proven to be advantageous in many applications compared with conventional bulk technology. However, image sensor integration on SOI substrates suffers from low quantum efficiency, which inhibits the development of SOI imaging systems. To overcome the barrier, CMOS compatible devices with self-amplification have been reported (Zhang et al. 1998; Yamamoto et al. 1996). However, the use of the high gain properties required a stable process and an accurate model for predicting the output, which are both not yet available. In this paper, we have investigated the performance of a hybrid active pixel structure. In this approach, the photodiode is built on the bottom substrate, while the reset transistor and the in-pixel amplifying transistor are built on the top silicon film. The performance of the APS is expected to be similar to the bulk technology, with potentially higher speed due to the lower capacitance that the photodiode has to drive in SOI technology. However, as a minimal deviation from the conventional SOI CMOS process is used to fabricate the APS, the photodiode is less optimized than current bulk technology. The operation of the APS in different configurations under different light intensities was studied and is reported.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134455770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Power amplifiers on thin-film-silicon-on-insulator (TFSOI) technology 基于薄膜绝缘体硅(TFSOI)技术的功率放大器

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819888

D. Ngo, W.M. Huang, J. Ford, D. Spooner

引用次数: 5

A RF power LDMOS device on SOI 一种基于SOI的射频功率LDMOS器件

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819870

J. Fiorenza, J. D. del Alamo, D. Antoniadis

引用次数: 9

Thin-layer SIMOX for future applications 用于未来应用的薄层SIMOX

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819875

M. Anc, R. Dolan, J. Jiao, T. Nakai

{"title":"Thin-layer SIMOX for future applications","authors":"M. Anc, R. Dolan, J. Jiao, T. Nakai","doi":"10.1109/SOI.1999.819875","DOIUrl":"https://doi.org/10.1109/SOI.1999.819875","url":null,"abstract":"Separation by implantation of oxygen (SIMOX) substrates implanted with stoichiometric doses of oxygen (1.8/spl times/10/sup 18/O/sup +//cm/sup 2/) at high energy (180-200 keV) and annealed at high temperatures have been accepted in silicon technology. Four times lower doses and extended annealing schemes were shown to form 100 nm thick buried oxides (Nakashima et al. 1993; Izumi, 1997) with application in commercial processes. The need for lower cost SOI wafers and thinner layers in future fully-depleted circuits continuously stimulates efforts to develop lower dose, thin buried oxide processes (Giles et al. 1994; Meyyappan et al. 1995; Holland et al. 1996). This work aims to demonstrate the formation of SIMOX layers in large area wafers with further reduced oxygen doses at energies below 100 keV. At the low energy peak of oxygen, the distribution is shallower and the full width at half maximum of this distribution is smaller than that for high energy implantation. Implantation at 65 keV generates near factor of 2 lower lattice damage per ion compared to 200 keV implantation. This allows more favorable conditions for formation of a stoichiometric buried oxide at low energy rather than at high energy. In addition, the manufacturability is improved due to the direct tailoring of the layer thickness for the criteria of fully depleted circuits at the basic process.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121114342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A dynamic body discharge technique for SOI circuit applications 用于SOI电路的动态体放电技术

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819861

J. Kuang, M. J. Saccamango, P. Lu, C. Chuang, F. Assaderaghi

引用次数: 13

A 0.5-V, 3-mW, 54/spl times/54-b multiplier with a triple-V/sub th/ CMOS/SIMOX circuit scheme 一个0.5 v, 3mw, 54/spl倍/54倍倍的倍频器，采用三v /sub / CMOS/SIMOX电路方案

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819859

K. Fujii, T. Douseki

{"title":"A 0.5-V, 3-mW, 54/spl times/54-b multiplier with a triple-V/sub th/ CMOS/SIMOX circuit scheme","authors":"K. Fujii, T. Douseki","doi":"10.1109/SOI.1999.819859","DOIUrl":"https://doi.org/10.1109/SOI.1999.819859","url":null,"abstract":"Summary form only given. Sub-1 V CMOS/SOI circuit technology is the most effective candidate for ultra-low-power applications in future ULSIs. We have proposed a triple-V/sub th/ CMOS/SIMOX circuit (Fujii et al., 1998; Douseki et al., 1998) that operates at an ultra low supply voltage of less than 0.5 V. The circuit consists of fully-depleted low- and medium-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power switch transistors. The low-V/sub th/ CMOS logic gates in critical paths and medium-V/sub th/ logic gates in noncritical paths achieve fast operation and leakage current reduction in the active mode. In addition, high-V/sub th/ power-switch transistors dramatically cut the leakage current in the standby mode. To improve circuit performance, the delay time of the critical path in the low-V/sub th/ logic blocks should be reduced and lowand medium-V/sub th/ logic gates should be assigned without any loss of speed. In this paper, we describe a triple-V/sub th/ 54/spl times/54-b multiplier that uses a 108-b adder with a source-controlled transmission-gate multiplexer in the critical path and a Wallace tree block in which low- and medium-V/sub th/ logic gates are automatically assigned using EDA tools.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130608210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Ultimately thin SOI MOSFETs: special characteristics and mechanisms 最终薄SOI mosfet:特殊的特性和机制

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819868

T. Ernst, D. Munteanu, S. Cristoloveanu, T. Ouisse, N. Hefyene, S. Horiguchi, Y. Ono, Y. Takahashi, K. Murase

引用次数: 24

Architecture and performance of 3-dimensional SOI circuits 三维SOI电路的结构与性能

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819850

R. Zhang, K. Roy, D. Janes

引用次数: 28