1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)最新文献_第3页

A SOI current memory for analog signal processing at high temperature 用于高温模拟信号处理的SOI电流存储器

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819837

L. Portmann, M. Declercq

引用次数: 1

Comparison between fully- and partially-depleted SOI MOSFET's for low-power radio-frequency applications 低功率射频应用中完全耗尽和部分耗尽SOI MOSFET的比较

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819839

O. Rozeau, J. Jomaah, C. Boussey, C. Raynaud, J. Pelloie, F. Balestra

引用次数: 4

Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture 埋藏氧化物边缘电容:一种新的物理模型及其对SOI器件规模和结构的影响

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819847

T. Ernst, S. Cristoloveanu

{"title":"Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture","authors":"T. Ernst, S. Cristoloveanu","doi":"10.1109/SOI.1999.819847","DOIUrl":"https://doi.org/10.1109/SOI.1999.819847","url":null,"abstract":"Fringing fields into the buried oxide and substrate depletion region stand as a key limiting factor for SOI MOSFET channel length reduction beyond 0.1 /spl mu/m. In fully-depleted (FD) SOI transistors, they cause a strong DIBL enhancement and a parasitic back channel conduction. On the other hand, in partially-depleted (PD) devices, the back channel control is even more difficult. The understanding and modeling of this phenomenon is of major interest, especially for RF SOI applications on high resistivity substrates where the depleted substrates behave as dielectrics. Various solutions to reduce these drawbacks are envisaged, such as buried oxide shrinking or double gate devices (Colinge, 1997; Cristoloveanu and Li, 1995). Thus far, the fringing field effect was ignored or merely included in FD analytical models by use of adjustable parameters. This paper presents a simple physical model for the evaluation of short channel effects induced by the BOX and substrate depletion. We analyze the lateral drain field penetration in the BOX and substrate, and calculate the related fringing capacitances. The model serves to anticipate the buried oxide scaling and substrate resistivity effects and to suggest the \"ground plane\" (GP) concept (Ernst and Cristoloveanu, 1999; Wong et al, 1998) as a suitable architecture for deep sub-micron SOI MOSFETs.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114312770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Scalability of fully-depleted SOI technology into 0.13 /spl mu/m 1.2 V-1 V CMOS generation 完全耗尽的SOI技术可扩展到0.13 /spl mu/m 1.2 V- 1v CMOS一代

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819865

C. Raynaud, O. Faynot, J. Pelloie, F. Martin, S. Tedesco, J. Cluzel, A. Grouillet, B. Dal'zotto, D. Vanhoenacker

{"title":"Scalability of fully-depleted SOI technology into 0.13 /spl mu/m 1.2 V-1 V CMOS generation","authors":"C. Raynaud, O. Faynot, J. Pelloie, F. Martin, S. Tedesco, J. Cluzel, A. Grouillet, B. Dal'zotto, D. Vanhoenacker","doi":"10.1109/SOI.1999.819865","DOIUrl":"https://doi.org/10.1109/SOI.1999.819865","url":null,"abstract":"Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS has been demonstrated for partially-depleted (PD) devices (Leobandung et al., 1998). Propagation delay versus active power can be greatly reduced by using fully-depleted (FD) devices, because threshold voltage (V/sub t/) and junction capacitance (increased by halo implant in case of bulk and PD devices) are lower. However, this advantage is possible only if transconductance is not degraded by high S/D resistance and if SCE and DIBL are well controlled, essentially by reducing silicon thickness. Furthermore, sensitivity of electrical parameters to silicon thickness (tsi) for FD devices is often mentioned as a critical process issue due to SOI substrate thickness nonuniformity. In this paper, we show (with both 2D simulations and measurements) that V/sub t/ control can be improved by a low energy S/D implant for enhancement-mode (EM) devices. S/D resistance can also be maintained at a low enough level by using a recessed-channel process, which allows the proper reduction of tsi exactly under the gate (Raynaud et al., 1998). Using a TiSi/sub 2/ salicide process on gate and elevated S/D regions, we have measured a maximum oscillation frequency f/sub max/ of 48 GHz at 0.9 V for 0.25 /spl mu/m NMOS. Finally, we show that, due to a balance between different physical effects, the distribution of critical parameters for digital applications (saturation and off currents, propagation delay and power consumption) is not degraded by silicon thickness nonuniformity.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124831423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Study of Cu diffusion in ultra thin bonded SOI wafers evaluated by using radioactive isotope tracers 用放射性同位素示踪剂评价超薄键合SOI晶圆中Cu的扩散

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819884

J. Furihata, M. Nakano, K. Mitani

引用次数: 2

High frequency losses in transmission lines made on SIMOX, bulk silicon and depleted silicon/silicon structures formed by wafer bonding 传输线中的高频损耗是由SIMOX、大块硅和晶圆键合形成的贫硅/硅结构造成的

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819843

M. Johansson, M. Bergh, S. Bengtsson

引用次数: 2

Thinning of Si in SOI wafers by the SC1 standard clean 用SC1标准清洗SOI硅片中的硅

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819879

G. Celler, D. Barr, J. Rosamilia

引用次数: 8

Circuit simulator and compact model requisites for accurate simulation of AC floating body behaviour in PD SOI 电路模拟器和紧凑的模型是精确模拟PD SOI交流浮体行为的必要条件

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819889

J. Benson, W. Redman-White, C. Easson, N. D'Halleweyn, M. Uren

引用次数: 0

High performance sub-0.1 /spl mu/m SOI polysilicon spacer gate MOSFETs using large angle tilted implant for drain engineering 用于排水工程的高性能0.1 /spl mu/m以下SOI多晶硅间隔栅mosfet采用大角度倾斜植入

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819869

K. To, J. Woo

{"title":"High performance sub-0.1 /spl mu/m SOI polysilicon spacer gate MOSFETs using large angle tilted implant for drain engineering","authors":"K. To, J. Woo","doi":"10.1109/SOI.1999.819869","DOIUrl":"https://doi.org/10.1109/SOI.1999.819869","url":null,"abstract":"With the boom in the wireless communications market, RF CMOS has attracted a great deal of interest because of its low cost and compatibility with logic circuits. The SOI substrate is especially robust in this case due to the low power nature originating from the reduced junction capacitances. To achieve the high operating frequency that is required in RF applications, it is important to have high transconductance, and this can be realized by reducing the gate length. However, shortening the gate length could meanwhile increase the gate resistance and thus degrade the unit power gain frequency. While the gate resistance can be reduced by using thicker silicide, this approach is not feasible wherever shallow junctions exist, as in the case of SOI and sub-0.1 /spl mu/m MOSFETs. In this regard, the polysilicon spacer gate structure (Kun H. To et al., 1998; Johnson et al., 1997) can provide the best solution. This structure, however, imposes a great problem for drain engineering when high performance is needed. In this work, a large tilt angle implant is proposed to implement the drain engineering. Due to the buried oxide, the drain junction depth is well controlled by the silicon film thickness and thus the short channel behaviour can be suppressed by using thinner Si films.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122327474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

"Gated-diode" in SOI MOSFETs: a sensitive tool for characterizing the buried Si-SiO/sub 2/ interface SOI mosfet中的“门控二极管”:用于表征埋置Si-SiO/sub - 2/接口的灵敏工具

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819854

Xuejun Zhao, D. Ioannou

{"title":"\"Gated-diode\" in SOI MOSFETs: a sensitive tool for characterizing the buried Si-SiO/sub 2/ interface","authors":"Xuejun Zhao, D. Ioannou","doi":"10.1109/SOI.1999.819854","DOIUrl":"https://doi.org/10.1109/SOI.1999.819854","url":null,"abstract":"Summary form only given. A critical factor in the development of SOI wafers and related CMOS technologies is the quality of the buried Si-SiO/sub 2/ interface. Careful wafer preparation is necessary to obtain reduced surface state density in order to suppress back channel leakage and improve hot carrier reliability and radiation hardness. However, the measurement of the back interface properties and in particular the interface state density remains one of the most difficult parameters to measure in SOI transistors. This is because the large thickness of the buried oxide (relative to gate oxide) renders the usual techniques insensitive and very difficult to apply (Ioannou et al., 1991; Wuters et al., 1989). There has recently been renewed interest in an old technique based on the gated-diode concept (Grove and Fitzelard, 1966), new refinements and modifications of which are being used for the study of current bulk CMOS technologies (Cai and Sah, 1999; Guan et al., 1999). The purpose of this paper is to explain how the presence of two channels makes the adaptation of this technique particularly useful for SOI MOSFETs and suitable for evaluation of the buried interface. The present approach is distinct from and complementary to a recently published modification of the gated-diode technique applied to dual-gate SOI devices for measurement of the recombination lifetime (Ernst et al., 1999).","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130737020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4