Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture

Fringing fields into the buried oxide and substrate depletion region stand as a key limiting factor for SOI MOSFET channel length reduction beyond 0.1 /spl mu/m. In fully-depleted (FD) SOI transistors, they cause a strong DIBL enhancement and a parasitic back channel conduction. On the other hand, in partially-depleted (PD) devices, the back channel control is even more difficult. The understanding and modeling of this phenomenon is of major interest, especially for RF SOI applications on high resistivity substrates where the depleted substrates behave as dielectrics. Various solutions to reduce these drawbacks are envisaged, such as buried oxide shrinking or double gate devices (Colinge, 1997; Cristoloveanu and Li, 1995). Thus far, the fringing field effect was ignored or merely included in FD analytical models by use of adjustable parameters. This paper presents a simple physical model for the evaluation of short channel effects induced by the BOX and substrate depletion. We analyze the lateral drain field penetration in the BOX and substrate, and calculate the related fringing capacitances. The model serves to anticipate the buried oxide scaling and substrate resistivity effects and to suggest the "ground plane" (GP) concept (Ernst and Cristoloveanu, 1999; Wong et al, 1998) as a suitable architecture for deep sub-micron SOI MOSFETs.