High performance sub-0.1 /spl mu/m SOI polysilicon spacer gate MOSFETs using large angle tilted implant for drain engineering

Abstract

With the boom in the wireless communications market, RF CMOS has attracted a great deal of interest because of its low cost and compatibility with logic circuits. The SOI substrate is especially robust in this case due to the low power nature originating from the reduced junction capacitances. To achieve the high operating frequency that is required in RF applications, it is important to have high transconductance, and this can be realized by reducing the gate length. However, shortening the gate length could meanwhile increase the gate resistance and thus degrade the unit power gain frequency. While the gate resistance can be reduced by using thicker silicide, this approach is not feasible wherever shallow junctions exist, as in the case of SOI and sub-0.1 /spl mu/m MOSFETs. In this regard, the polysilicon spacer gate structure (Kun H. To et al., 1998; Johnson et al., 1997) can provide the best solution. This structure, however, imposes a great problem for drain engineering when high performance is needed. In this work, a large tilt angle implant is proposed to implement the drain engineering. Due to the buried oxide, the drain junction depth is well controlled by the silicon film thickness and thus the short channel behaviour can be suppressed by using thinner Si films.