A low power /spl Sigma//spl Delta/ analog-to-digital modulator with 50 MHz sampling rate in a 0.25 /spl mu/m SOI CMOS technology

Abstract

A second-order double-sampled analog-to-digital /spl Sigma//spl Delta/ modulator is implemented in a 0.25 /spl mu/m fully-depleted silicon-on-insulator (FDSOI) CMOS process. FDSOI has a better subthreshold swing and reduced short-channel effect compared to traditional bulk CMOS, and therefore the threshold voltage and hence the supply voltage can be lowered for low power applications.