Shaghayegh Mesforush, Alba Cazorla, Hayley Melville, Philippe Blanchard, Hagen Klauk, Ute Zschieschang, Min Zhang, Lamiaa Fijahi, Marta Mas‐Torrent, Esther Barrena
{"title":"Gate‐Dielectric Surface Engineering With Fluorinated Monolayers: Minimizing Contact Resistance and Nonidealities in OFETs","authors":"Shaghayegh Mesforush, Alba Cazorla, Hayley Melville, Philippe Blanchard, Hagen Klauk, Ute Zschieschang, Min Zhang, Lamiaa Fijahi, Marta Mas‐Torrent, Esther Barrena","doi":"10.1002/aelm.202500260","DOIUrl":"https://doi.org/10.1002/aelm.202500260","url":null,"abstract":"Organic field‐effect transistors (OFETs) hold great potential for flexible, large‐area electronics, but face challenges related to hysteresis in the transfer characteristics, contact resistance, and charge trapping. This study examines the growth and electrical properties of 2‐decyl‐7‐phenyl[1]benzothieno[3,2‐b][1]benzothiophene (Ph‐BTBT‐10) organic‐semiconductor films on <jats:italic>Al</jats:italic><jats:sub>2</jats:sub><jats:italic>O</jats:italic><jats:sub>3</jats:sub> as gate dielectric, focusing on the effects of surface functionalization with a self‐assembled monolayer (SAM) of either a non‐fluorinated or a more or less strongly fluorinated phosphonic acid. This functionalization of the gate dielectric surface is found not to significantly affect the structural organization of Ph‐BTBT‐10 thin films grown at room temperature. Thin films grown at room temperature exhibit a single‐layer lamella with a step height of 26.7 Å, although there is evidence of a bilayer arrangement at the semiconductor‐dielectric interface. Remarkably, the use of <jats:italic>Al</jats:italic><jats:sub>2</jats:sub><jats:italic>O</jats:italic><jats:sub>3</jats:sub> functionalized with a fluorinated SAM leads to significant improvements in OFET performance, including near‐zero threshold voltages, reduced hysteresis, reduced contact resistance, and more ideal electrical characteristics compared to bare <jats:italic>Al</jats:italic><jats:sub>2</jats:sub><jats:italic>O</jats:italic><jats:sub>3</jats:sub>. This work highlights the significant yet non‐trivial benefits of gate‐dielectric surface functionalization in reducing contact resistance and mitigating non‐ideal behaviors in OFETs, offering an alternative to traditional approaches like contact doping or functionalization of the source/drain contacts in bottom‐contact organic thin‐film transistors (TFTs).","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"22 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144995230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shengyu Yang, Peng Wu, Yanfei Sheng, Yiwen Dong, Zhiwei Li, Tao Wang, Liang Qiao, Fashen Li
{"title":"On the Quality Criteria for Microwave Absorbing Materials (Adv. Electron. Mater. 14/2025)","authors":"Shengyu Yang, Peng Wu, Yanfei Sheng, Yiwen Dong, Zhiwei Li, Tao Wang, Liang Qiao, Fashen Li","doi":"10.1002/aelm.70084","DOIUrl":"10.1002/aelm.70084","url":null,"abstract":"<p><b>Microwave Absorbing Materials</b></p><p>In this cover image, the main focus is an atomic layer atop an electromagnetic wave-absorbing device layer, illustrating the core concept of the work: establishing the relationship between absorbing materials and absorbing devices. When an electromagnetic wave is incident on the material, the device layer reflects three distinct matching mechanisms–perfect matching, partial matching, and mismatch–closely tied to the discussions in article 10.1002/aelm.202500239 by Liang Qiao, Fashen Li, and co-workers.\u0000\u0000 <figure>\u0000 <div><picture>\u0000 <source></source></picture><p></p>\u0000 </div>\u0000 </figure></p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 14","pages":""},"PeriodicalIF":5.3,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://advanced.onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.70084","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144995753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vilas Patil, Hazel Neill, Brendan Sheehan, Paul K. Hurley, Lida Ansari, Farzan Gity
{"title":"Dopingless Ambipolar Field‐Effect Transistors Based on MoTe2 2D Material for CMOS Nanoelectronics","authors":"Vilas Patil, Hazel Neill, Brendan Sheehan, Paul K. Hurley, Lida Ansari, Farzan Gity","doi":"10.1002/aelm.202500305","DOIUrl":"https://doi.org/10.1002/aelm.202500305","url":null,"abstract":"The charge transport characteristics of ambipolar MoTe<jats:sub>2</jats:sub> field‐effect transistors (FETs), with the entire MoTe<jats:sub>2</jats:sub> channel exposed to ambient air, across varying temperature conditions, are experimentally and theoretically investigated. These FETs exhibit stable transport behavior without the need for complex surface encapsulation. This finding is significant as it eliminates the need for external and intentional n‐type and p‐type doping, addressing a major challenge in integrating 2D materials into complementary metal‐oxide‐semiconductor (CMOS) technology. The first‐principles simulations provide insights into the electronic properties and band alignment at the Ni/MoTe<jats:sub>2</jats:sub> interface, revealing the fundamental mechanism behind the observed ambipolar transport response. Through temperature‐dependent electrical characterization, hysteresis, threshold voltage shifts, and carrier mobility variations are investigated, providing a deeper understanding of MoTe<jats:sub>2</jats:sub>/SiO<jats:sub>2</jats:sub> interface interactions. The results indicate that at elevated temperatures, charge trapping and phonon scattering lead to reduced carrier mobility and ON/OFF current ratio, which are primarily driven by interface interactions rather than material impurities. Importantly, the devices achieve stable performance despite direct exposure to ambient conditions, demonstrating their robustness without complex passivation techniques. Further optimization of passivation and encapsulation strategies can enhance performance, including carrier mobility improvement. This work demonstrates the potential of FETs based on MoTe<jats:sub>2</jats:sub>, offering a promising pathway for next‐generation CMOS nanoelectronics.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"63 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144930611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Andrea Sessa, Tsotne Dadiani, Sebastiano De Stefano, Ofelia Durante, Aniello Pelella, Catalin Parvulescu, Adrian Dinescu, Martino Aldrigo, Chia‐Nung Kuo, Chin Shan Lue, Gianluca D'Olimpio, Enver Faella, Antonio Politano, Maurizio Passacantando, Antonio Di Bartolomeo
{"title":"Ultrathin SnS2 Field‐Effect Transistors Exhibiting Temperature‐Enhanced Memory Performance","authors":"Andrea Sessa, Tsotne Dadiani, Sebastiano De Stefano, Ofelia Durante, Aniello Pelella, Catalin Parvulescu, Adrian Dinescu, Martino Aldrigo, Chia‐Nung Kuo, Chin Shan Lue, Gianluca D'Olimpio, Enver Faella, Antonio Politano, Maurizio Passacantando, Antonio Di Bartolomeo","doi":"10.1002/aelm.202500327","DOIUrl":"https://doi.org/10.1002/aelm.202500327","url":null,"abstract":"Tin disulfide (SnS<jats:sub>2</jats:sub>) is a 2D semiconductor with a wide bandgap exceeding 2.0 eV. A detailed electrical study of back‐gated Schottky‐barrier field‐effect transistors (FETs) based on multilayer SnS<jats:sub>2</jats:sub> channels is presented. The devices display n‐type conduction, with current levels increasing with temperature due to thermally activated transport across the contacts. A pronounced hysteresis appears in the transfer characteristics, growing linearly with temperature at a rate of ≈0.5 V K<jats:sup>−1</jats:sup>, revealing a temperature‐sensitive response that can be explored for sensing functionalities. Remarkably, the same temperature dependence enhances the memory functionality of the devices: the memory window broadens with increasing temperature, and both retention and endurance improve, in contrast to conventional memory technologies. The observed behavior is linked to the modulation of carrier transport at the contacts, where environmental exposure induces barrier asymmetries and inhomogeneities, as confirmed by analysis using the Güttler–Werner model. These results suggest that SnS<jats:sub>2</jats:sub>‐based FETs may be exploited either for sensing or memory functionality, depending on the operating conditions, outlining a conceptual route toward compact and reconfigurable components in future 2D electronic systems.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"32 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144930549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Laura Teuerle, Tommy Meier, Klara Hänisch, Finn Jaekel, Yeohoon Yoon, Andreas Wendel, Hans Kleemann
{"title":"Life‐Cycle Assessment of Printed Electronic Components ‐ Case Study for Organic Electrochemical Transistors","authors":"Laura Teuerle, Tommy Meier, Klara Hänisch, Finn Jaekel, Yeohoon Yoon, Andreas Wendel, Hans Kleemann","doi":"10.1002/aelm.202500372","DOIUrl":"https://doi.org/10.1002/aelm.202500372","url":null,"abstract":"To ensure sustainable progress, future electronics must prioritize both performance and environmental impact, explaining the interest in flexible and printed electronics. However, the sustainability claims often connected to the field of flexible and printed electronics must to be substantiated using analytic methods, providing the motivation for quantitative Life‐Cycle Assessment (LCA). Here, a practical guide is provided for researchers from the field to implement early‐stage LCA in parallel to their technological development. An Organic Electronic Transistor (OECT) is selected for the case study, and a comprehensive Life‐Cycle Inventory is developed based on a modular Process of Record (PoR). Due to the plethora of different materials and processes available (e.g., printing, lithography, parylene peel‐off), the modular and adaptable PoR framework enables researchers to use this database for their own devices beyond the OECT example used here. The inventory list is made open‐access, and the research community is invited to contribute and expand the inventory list. By making LCA a standard tool in printed electronics, the community can move beyond sustainability claims to measurable environmental impact, driving truly responsible innovation in electronics.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"24 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144930610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lekai Song, Pengyu Liu, Yang Liu, Jingfang Pei, Wenyu Cui, Songwei Liu, Yingyi Wen, Teng Ma, Kong‐Pang Pun, Leonard W. T. Ng, Guohua Hu
{"title":"Hardware Implementation of Bayesian Decision‐Making with Memristors","authors":"Lekai Song, Pengyu Liu, Yang Liu, Jingfang Pei, Wenyu Cui, Songwei Liu, Yingyi Wen, Teng Ma, Kong‐Pang Pun, Leonard W. T. Ng, Guohua Hu","doi":"10.1002/aelm.202500134","DOIUrl":"https://doi.org/10.1002/aelm.202500134","url":null,"abstract":"Brains perform decision‐making by Bayes theorem – events are quantified as probabilities and based on probability rules, computed to render the decisions. Learning from this, Bayes theorem may be applied to enable efficient user–scene interactions. However, given the probabilistic nature, implementing Bayes theorem with the conventional deterministic computing hardware can incur excessive computational cost and decision latency. Though challenging, here a probabilistic computing approach is presented based on memristors to implement Bayes theorem. Memristors are integrated with Boolean logic circuits and, by exploiting the volatile stochastic switching of the memristors, realize probabilistic Boolean logic operations, key for Bayes theorem hardware implementation. To empirically validate the efficacy of the hardware Bayes theorem in enabling user–scene interactions, lightweight Bayesian inference and fusion operators are designed using the probabilistic logic circuits and apply the operators in road scene parsing for self‐driving, including route planning and obstacle detection. The results show the operators can achieve reliable decisions in less than 0.4 ms (or equivalently 2500 fps), outperforming human decision‐making and the existing driving assistance systems.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"31 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144927986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimizing the Thermal Conductivity of 2D Materials/Copper Composites through Strain‐Controlled Electron‐Phonon Coupling Effect","authors":"Tianyu Zhao, Baishan Liu, Yalun Wang, Juncai Liang, Zhongzheng Pei, Xiaohui Zhang","doi":"10.1002/aelm.202500133","DOIUrl":"https://doi.org/10.1002/aelm.202500133","url":null,"abstract":"In recent years, 5G mobile communication technology, high‐power devices, and micro‐integrated electronic devices have developed and iterated rapidly. However, the heat generation of the devices cannot be ignored under such high‐power consumption, which affects their normal operation and decreases the lifetime, or even causes damage in severe cases. Copper is the most widely used heat conducting material in electronic devices, but further improvement of its thermal properties to match the demand is still a crucial challenge. Graphene with ultra‐high theoretical thermal conductivity is an ideal material to be combined with copper to improve its thermal conductivity, but the introduced graphene/copper interfaces bring phonon/electron scattering, which limits the heat transfer. In this work, laminated graphene‐copper composites (HP‐GCCs) are prepared by a hot‐pressing strategy, the graphene/copper interfaces can form a stress‐induced phonon‐electron coupling effect through controlling the graphene distribution, which can improve the phonon‐electron transmission of the interfaces and thus improve its thermal conductivity. The HP‐GCCs exhibit a high thermal conductivity of 440.60 W m<jats:sup>−1</jats:sup>·K<jats:sup>−1</jats:sup>, showing reduced temperature‐rise and improved efficiency when applied to devices in the practical applications. The investigations of the optimized graphene distribution of the composites through analyzing the mechanism of interfacial heat conduction provide valuable guidance for optimizing the synthesis and properties of 2D materials/copper composites.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"56 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144910809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiao Qing Chen, Lei Zhang, Yi Ning Zheng, Bing Bing Zhu, Marco Rossi, Giuseppe Castaldi, Shuo Liu, Vincenzo Galdi, Tie Jun Cui
{"title":"Non‐Uniform Space‐Time‐Coding Modulation for Low‐Complexity Diagnostics of Reconfigurable Intelligent Surfaces","authors":"Xiao Qing Chen, Lei Zhang, Yi Ning Zheng, Bing Bing Zhu, Marco Rossi, Giuseppe Castaldi, Shuo Liu, Vincenzo Galdi, Tie Jun Cui","doi":"10.1002/aelm.202500350","DOIUrl":"https://doi.org/10.1002/aelm.202500350","url":null,"abstract":"Reconfigurable intelligent surfaces (RISs) have emerged as a key enabler and promising technology for the next‐generation wireless communications by offering fine‐grained and dynamic control over electromagnetic wave propagation. However, achieving optimal and reliable performance in RIS‐assisted systems critically depends on the accurate diagnostics of faulty RIS elements. This paper proposes a novel RIS diagnostics method based on non‐uniform space‐time‐coding modulation that enables fault detection using <jats:italic>amplitude‐only</jats:italic> spectral measurements, eliminating the need for complex phase retrieval, coherent detection, or channel estimation. The approach involves applying a common time‐coding sequence across all RIS elements, while individually modulating each element with a unique, non‐uniform frequency. This establishes a one‐to‐one correspondence between the harmonic components in the reflected signal and the respective RIS elements. Faulty elements can be accurately identified by analyzing deviations in the measured harmonic amplitude distribution of these harmonics at their assigned modulation frequencies. Both simulation and experimental results demonstrate that the proposed method reliably detects faulty RIS elements with minimal measurement complexity, offering a computationally efficient alternative to existing diagnostic techniques.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"28 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144906084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gyeong Seop Kim, Jin Hyuk Choi, Min‐gu Kim, Ji‐Hoon Kang, Young Tack Lee
{"title":"Versatile Contact Engineering on β‐Ga2O3 Using EGaIn for Schottky Diodes and MESFET Applications","authors":"Gyeong Seop Kim, Jin Hyuk Choi, Min‐gu Kim, Ji‐Hoon Kang, Young Tack Lee","doi":"10.1002/aelm.202500332","DOIUrl":"https://doi.org/10.1002/aelm.202500332","url":null,"abstract":"Beta gallium oxide (β‐Ga<jats:sub>2</jats:sub>O<jats:sub>3</jats:sub>) has emerged as a promising ultrawide bandgap n‐type semiconductor for large‐area circuit integration and high‐power device applications in the field of 5G and AI technology. However, β‐Ga<jats:sub>2</jats:sub>O<jats:sub>3</jats:sub> has a critical problem in Ohmic contact formation using a traditional metallization method. In this study, a low‐temperature fabrication strategy is successfully demonstrated of an Ohmic contact electrode, employing eutectic gallium indium (EGaIn) liquid metal on β‐Ga<jats:sub>2</jats:sub>O<jats:sub>3</jats:sub> active channel material for Schottky diode circuit and metal semiconductor field effect transistor (MESFET) applications. The selective screen‐printing of Ohmic and rectifying contacts enables monolithic integration of symmetric and asymmetric device architectures, including source/drain electrodes, Schottky diodes, and FETs without additional post‐thermal annealing and etching processes. The β‐Ga<jats:sub>2</jats:sub>O<jats:sub>3</jats:sub>/Au Schottky diodes exhibit good rectifying properties of a current on/off ratio of 10⁷ and an ideality factor (η) of 1.63, while the MESFET devices demonstrate a drain current on/off ratio of ≈3.1 × 10<jats:sup>6</jats:sup>.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"50 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144906086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Controlling Bias Field of Pinned Layer Stacks for Double‐Pinned‐Layer Magnetic Tunnel Junction for STT‐MRAM","authors":"Shujun Ye, Koichi Nishioka","doi":"10.1002/aelm.202500132","DOIUrl":"https://doi.org/10.1002/aelm.202500132","url":null,"abstract":"Double‐pinned‐layer Magnetic Tunnel Junction (Double PL MTJ) enhances spin‐transfer‐torque magneto‐resistive random‐access memory (STT‐MRAM) performance by requiring anti‐parallel magnetization between both PLs at free layer interfaces and minimizing magnetostatic bias field (<jats:italic>H</jats:italic><jats:sub>bias</jats:sub>) from both PLs to enable reliable switching. In this study, a numerical method is established to accurately calculate <jats:italic>H</jats:italic><jats:sub>bias</jats:sub> and investigate PL designs that simultaneously fulfill both conditions. Among the configurations examined, a bottom PL composed of anti‐parallel (AP) coupled three magnetic layers (FM1, FM2, and FM3) combined with a top PL consisting of two such layers (FM4 and FM5) is identified a optimal. This configuration achieved the desired anti‐parallel magnetization at FL interfaces and effectively suppressed <jats:italic>H</jats:italic><jats:sub>bias</jats:sub>. The proposed structure enables a robust design strategy for Double PL MTJ, addressing key limitations such as high write current and paving the way for MTJ for large‐scale application in STT‐MRAM.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"71 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144906085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}