Recent Progress in Sub-10 Nm Nanofabrication for Scaling Down 2D Transistors

IF 5.3 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY
Haichuan Li, Yongyu Wu, Dawei Gao, Kai Xu, Kun Ren, Dianyu Qi
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Abstract

2D field-effect transistors (2D-FETs) leverage atomically thin, dangling-bond-free channels to overcome short-channel effects and surface defects in sub-10 nm nodes. However, conventional lithography hardly meets the requirement of sub-10 nm nanofabrication because of resolution limits, making the fabrication of 2D-FETs with sub-10 nm channel lengths still a significant challenge. Here, strategies of realizing 2D-FETs are reviewed with sub-10 nm channels: i) Ultraprecise nanolithography, including electron-beam lithography, cold development, and block copolymers (BCP)-based directed self-assembly (DSA); ii) Nanogap formation, leveraging stress-induced cracking, grain-boundary widening, electromigration, carbon-nanotube masking, and shadow evaporation; iii) Vertical-channel architectures, where channel length is defined by dielectric thickness in metal–insulator–metal stacks or barristor structures; iv) Self-aligned isolation, employing ultrathin film oxidation, adhesion lithography, and heterostructure undercut processes to precisely define source-drain separations. Key performance metrics are compiled and compared—contact resistance, on-state current, off-state leakage, DIBL, and subthreshold swing—across representative devices, illustrating the robust scaling immunity of 2D materials. Finally, emerging “lab-to-fab” approaches are discussed, such as edge lithography, mechanical cracking, and post-pattern modification, pointing toward scalable, low-cost manufacturing of wafer-scale sub-10 nm 2D-FETs. This outlook provides practical guidelines for future integrated circuit implementations based on 2D semiconductors.

Abstract Image

用于缩小二维晶体管尺寸的10纳米以下纳米加工的最新进展
2D场效应晶体管(2D- fet)利用原子薄的无悬键沟道来克服短沟道效应和10纳米以下节点的表面缺陷。然而,由于分辨率的限制,传统的光刻技术很难满足亚10nm纳米制造的要求,使得通道长度低于10nm的2d - fet的制造仍然是一个重大挑战。本文综述了利用亚10nm通道实现二维场效应管的策略:i)超精密纳米光刻技术,包括电子束光刻、冷显影和基于嵌段共聚物(BCP)的定向自组装(DSA);ii)纳米隙的形成,利用应力诱导的开裂、晶界扩大、电迁移、碳纳米管掩蔽和阴影蒸发;iii)垂直通道结构,其中通道长度由金属-绝缘体-金属堆叠或电阻器结构中的介电厚度定义;iv)自对准隔离,采用超薄膜氧化、附着光刻和异质结构切边工艺来精确定义源-漏分离。编制并比较了关键性能指标——接触电阻、导通状态电流、关断状态泄漏、DIBL和亚阈值跨摆代表性器件,说明了2D材料的鲁棒抗阻性。最后,讨论了新兴的“实验室到晶圆厂”方法,如边缘光刻,机械开裂和后模式修改,指向可扩展的,低成本的晶圆级10纳米以下2d - fet制造。该展望为未来基于二维半导体的集成电路实现提供了实用指南。
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来源期刊
Advanced Electronic Materials
Advanced Electronic Materials NANOSCIENCE & NANOTECHNOLOGYMATERIALS SCIE-MATERIALS SCIENCE, MULTIDISCIPLINARY
CiteScore
11.00
自引率
3.20%
发文量
433
期刊介绍: Advanced Electronic Materials is an interdisciplinary forum for peer-reviewed, high-quality, high-impact research in the fields of materials science, physics, and engineering of electronic and magnetic materials. It includes research on physics and physical properties of electronic and magnetic materials, spintronics, electronics, device physics and engineering, micro- and nano-electromechanical systems, and organic electronics, in addition to fundamental research.
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