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Lanthanide-Doped Ga2O3: A Route to Bandgap Engineering for Ultraviolet Detection
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-05 DOI: 10.1002/aelm.202500030
Shunze Huang, Xuefang Lu, Yinlong Cheng, Jianzhong Xu, Xin Qian, Feng Huang, Richeng Lin
{"title":"Lanthanide-Doped Ga2O3: A Route to Bandgap Engineering for Ultraviolet Detection","authors":"Shunze Huang, Xuefang Lu, Yinlong Cheng, Jianzhong Xu, Xin Qian, Feng Huang, Richeng Lin","doi":"10.1002/aelm.202500030","DOIUrl":"https://doi.org/10.1002/aelm.202500030","url":null,"abstract":"The demand for next-generation wide bandgap semiconductors is driven by applications such as solar-blind ultraviolet detection and ultra-high power electronics, and gallium oxide (Ga<sub>2</sub>O<sub>3</sub>) has emerged as a highly promising candidate material due to its ultra-wide bandgap, high intrinsic breakdown field strength, and quite significant ultraviolet absorption. However, the lack of doping engineering based on substituting isovalent elements to achieve bandgap tuning has limited the development of Ga<sub>2</sub>O<sub>3</sub> in ultraviolet detection. Here, the trivalent lanthanide elements are used as the homovalent substitution of gallium in Ga<sub>2</sub>O<sub>3</sub> to achieve effective regulation of the optical bandgap. The theoretical calculation shows that the doped lanthanide (Lu) introduces its 6s orbital electrons to the conduction band of Ga<sub>2</sub>O<sub>3</sub>, resulting in a significant shift of the conduction band. Furthermore, an ITO/Ga<sub>2</sub>O<sub>3</sub>:Ln/Au structure photodetector is prepared by Ga<sub>2</sub>O<sub>3</sub>:Lu thin films, which exhibits an ultra-low dark current (−2.09 × 10<sup>−</sup>¹<sup>3</sup> A) and a fast response speed (321/136.8 ms), demonstrating the great prospect of Ga<sub>2</sub>O<sub>3</sub>:Ln semiconductors in photoelectronics.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"73 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143782868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dopant Diffusion-Induced Dielectric Breakdown: Stacked Dielectric Reliability on Heavily Doped Polysilicon
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-05 DOI: 10.1002/aelm.202500046
Shuo Wang, Zebin Kong, Jie Zhao, Shukai Guan, Ranran Zhao, Anan Ju, Kunshu Wang, Pengfei Lian
{"title":"Dopant Diffusion-Induced Dielectric Breakdown: Stacked Dielectric Reliability on Heavily Doped Polysilicon","authors":"Shuo Wang, Zebin Kong, Jie Zhao, Shukai Guan, Ranran Zhao, Anan Ju, Kunshu Wang, Pengfei Lian","doi":"10.1002/aelm.202500046","DOIUrl":"https://doi.org/10.1002/aelm.202500046","url":null,"abstract":"This study identifies a novel failure mode in silicon dioxide/silicon nitride (SiO₂/Si₃N₄) capacitors caused by dopant diffusion in heavily doped polysilicon substrates. Under identical thermal oxidation conditions, the interfacial oxide layer is significantly thinner on p type polysilicon compared to n type polysilicon. N type capacitors exhibit superior performance, with a breakdown voltage of 88 V, whereas p type capacitors demonstrate lower breakdown voltage of 51 V. The time-dependent dielectric breakdown (TDDB) analysis indicates that n type capacitors exhibit lifetimes exceeding 10 years under high-voltage stress at 125 °C. In contrast, p type capacitors demonstrate rapid failure when subjected to a voltage of 30 V. Conduction analysis reveals that Poole–Frenkel conduction dominates the stacked dielectric layers, but thinning of the interfacial oxide layer significantly increases Fowler–Nordheim tunneling, ultimately driving stacked dielectric breakdown. These findings highlight the critical role of dopant diffusion in interfacial oxide reliability and provide insights for improving the performance of high-k stacked dielectrics in heavily doped polysilicon.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"59 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143782867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Highly Stretchable LED Display Using Liquid Metal and Molybdenum-Barriered Multilayer Electrodes with Long-Term Reliability (Adv. Electron. Mater. 4/2025)
IF 5.3 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-03 DOI: 10.1002/aelm.202570012
Masashi Miyakawa, Hiroshi Tsuji, Tatsuya Takei, Toshihiro Yamamoto, Yoshihide Fujisaki, Mitsuru Nakata
{"title":"Highly Stretchable LED Display Using Liquid Metal and Molybdenum-Barriered Multilayer Electrodes with Long-Term Reliability (Adv. Electron. Mater. 4/2025)","authors":"Masashi Miyakawa,&nbsp;Hiroshi Tsuji,&nbsp;Tatsuya Takei,&nbsp;Toshihiro Yamamoto,&nbsp;Yoshihide Fujisaki,&nbsp;Mitsuru Nakata","doi":"10.1002/aelm.202570012","DOIUrl":"10.1002/aelm.202570012","url":null,"abstract":"<p><b>Highly Stretchable LED Displays</b></p><p>In article number 2400676, Yang Bai and co-workers demonstrate a highly stretchable LED display using liquid metal and molybdenum-barriered multilayer electrodes. This technology enables high reliability as well as high stretchability under repeated deformation of 12,000 times and long-term stability over 300 days.\u0000\u0000 <figure>\u0000 <div><picture>\u0000 <source></source></picture><p></p>\u0000 </div>\u0000 </figure></p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 4","pages":""},"PeriodicalIF":5.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202570012","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143767036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Configuration and Charge Dynamics of Defect-Cluster-Dipoles in CaTiO3 for Enhanced Permittivity
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-03 DOI: 10.1002/aelm.202500145
Jian Wang, Zhuowen Zou, Jiajun Zhu, Dandan Gao, Wanbiao Hu
{"title":"Configuration and Charge Dynamics of Defect-Cluster-Dipoles in CaTiO3 for Enhanced Permittivity","authors":"Jian Wang, Zhuowen Zou, Jiajun Zhu, Dandan Gao, Wanbiao Hu","doi":"10.1002/aelm.202500145","DOIUrl":"https://doi.org/10.1002/aelm.202500145","url":null,"abstract":"The wealth of complex defects induces attractive functionalities and structural variations in materials. This renders engineering defect states, as well as building up a defect-property relationship, a central subject, but it remains highly challenging because the configurations and charge dynamics of the involved defect systems are hardly explored and thus unclear experimentally. Herein, the defect-dipole-cluster in La-doped CaTiO<sub>3</sub> and, more importantly, its dielectric response process is clarified. Through combined HAADF-STEM, DFT calculation, dielectric, and photoluminescence (PL) spectroscopy, the defect configuration is identified to be <i>V</i><sub><b>Ca</b></sub> − <b>O</b><sup>−</sup> − <b>La</b><sub><b>Ca</b></sub> type defect-cluster-dipole. The electron–hole recombination from the Ti<sup>3+</sup> and O<sup>−</sup> states dominates the dielectric relaxation process, as revealed by the similar relaxation frequencies of dielectric response and photoluminescence emission. These findings experimentally demonstrate property tailoring involved in defect-cluster-dipole, providing crucial insights for establishing the defect-property relationship in dielectric materials.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"21 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143767037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual-Layer-Per-Array Operation Using Local Polarization Switching of Ferroelectric Tunnel FETs for Massive Neural Networks (Adv. Electron. Mater. 4/2025)
IF 5.3 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-03 DOI: 10.1002/aelm.202570011
Jae Seung Woo, Chae Lin Jung, Jin Ho Chang, Minjeong Ryu, Woo Young Choi
{"title":"Dual-Layer-Per-Array Operation Using Local Polarization Switching of Ferroelectric Tunnel FETs for Massive Neural Networks (Adv. Electron. Mater. 4/2025)","authors":"Jae Seung Woo,&nbsp;Chae Lin Jung,&nbsp;Jin Ho Chang,&nbsp;Minjeong Ryu,&nbsp;Woo Young Choi","doi":"10.1002/aelm.202570011","DOIUrl":"https://doi.org/10.1002/aelm.202570011","url":null,"abstract":"<p><b>Dual-Layer-Per-Array Operations</b></p><p>In article number 2400606, Woo Young Choi and co-workers propose and implement a novel dual-layer-per-array operation in a FeTFET array for large-scale neural network implementations. Owing to independently controllable two current regions, dual-layer vector-matrix multiplication operations can be performed within a single FeTFET synapse array, enabling identical neural network implementation in half the area of the conventional neuromorphic hardware.\u0000\u0000 <figure>\u0000 <div><picture>\u0000 <source></source></picture><p></p>\u0000 </div>\u0000 </figure></p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 4","pages":""},"PeriodicalIF":5.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202570011","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-03 DOI: 10.1002/aelm.202500031
Kiyung Kim, Minjae Kim, Yongsu Lee, Hae-Won Lee, Jae Hyeon Jun, Jun-Hyeok Choi, Seongbeen Yoon, Hyeon-Jun Hwang, Byoung Hun Lee
{"title":"Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor","authors":"Kiyung Kim, Minjae Kim, Yongsu Lee, Hae-Won Lee, Jae Hyeon Jun, Jun-Hyeok Choi, Seongbeen Yoon, Hyeon-Jun Hwang, Byoung Hun Lee","doi":"10.1002/aelm.202500031","DOIUrl":"https://doi.org/10.1002/aelm.202500031","url":null,"abstract":"The complementary field-effect transistor (CFET) structure is a highly area-efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recrystallization, which has been limiting further development. In this paper, an alternative method is proposed to realize CFETs using p-type tellurium (Te) (for the lower-level channel) and n-type zinc oxide (ZnO) (for the upper-level channel). Te and ZnO are directly deposited on a 30 × 30 mm<sup>2</sup> SiO<sub>2</sub>/Silicon substrate, using a considerably low-temperature fabrication process (&lt;150 °C). The lower p-type channel exhibits superior mobility exceeding 10 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup> even after the integration of the entire CFET process. The CFET inverter demonstrates a voltage gain &gt;51 at <i>V</i><sub>DD</sub> = 4 V and noise margins of 0.36 and 0.45 V at <i>V</i><sub>DD</sub> = 1 V. Using the same integration process, functional NAND and NOR logic gates are successfully demonstrated in the vertically integrated CFET structure. The proposed ZnO/Te CFET can be a promising device technology, particularly for 3D and heterojunction integration requiring a low thermal budget.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"23 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143767139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Solution-Shearing of Highly Smooth Ion-Gel Thin Films: Facilitating the Deposition of Organic Semiconductors for Ion-Gated Organic Field Effect Transistors
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-03 DOI: 10.1002/aelm.202400312
Jonathan Perez Andrade, Angelika Wrzesińska-Lashkova, Anupam Prasoon, Felix Talnack, Katherina Haase, Bernd Büchner, Xinliang Feng, Yana Vaynzof, Mike Hambsch, Yulia Krupskaya, Stefan C. B. Mannsfeld
{"title":"Solution-Shearing of Highly Smooth Ion-Gel Thin Films: Facilitating the Deposition of Organic Semiconductors for Ion-Gated Organic Field Effect Transistors","authors":"Jonathan Perez Andrade, Angelika Wrzesińska-Lashkova, Anupam Prasoon, Felix Talnack, Katherina Haase, Bernd Büchner, Xinliang Feng, Yana Vaynzof, Mike Hambsch, Yulia Krupskaya, Stefan C. B. Mannsfeld","doi":"10.1002/aelm.202400312","DOIUrl":"https://doi.org/10.1002/aelm.202400312","url":null,"abstract":"A straightforward method is developed to produce ion-gels (IGs) with surface roughness at the nanometer level using a solution-shearing process, enabling the first successful growth of crystalline, small-molecule organic semiconductor (OSC) films directly on the IG layer. The effectiveness of this approach is demonstrated by fabricating top-contact electrolyte-gated organic field-effect transistors (EGOFETs) using thermal vapor deposition and solution-shearing. The gel matrix consists of polymethyl methacrylate (PMMA) or its blend with poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF:HFP), and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]) serves as ionic liquid. X-ray photoemission spectroscopy (XPS) reveals that the shearing speed controls the polymer phase separation in the blended gels, producing capacitance values of up to 10.1 µF cm<sup>−</sup><sup>2</sup>. The exceptional smoothness of the gel films permits vacuum deposition polycrystalline films of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophen (C8-BTBT), dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophen (DNTT), and 2,9-didecyldinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C10-DNTT), and solution-shearing of C8-BTBT and 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) on their surfaces. Grazing incidence wide-angle X-ray scattering (GIWAXS) can now be conducted directly on the OSC films without obstruction by the gel. EGOFETs with minimal hysteresis and mobilities up to 1.46 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup> are obtained for C10-DNTT. This study underscores the possibility of producing transistor-grade polycrystalline organic semiconductor films on top of IGs, making them attractive for surface characterization techniques and in situ measurements.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"108 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143776052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monolithic 3D Logic Gates Based on p-Te and n-Bi2S3 Complementary Thin-Film Transistors
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-02 DOI: 10.1002/aelm.202400786
Yuqia Ran, Yiwen Song, Long Li, Xujin Song, Pingfan Gu, Qi Wang, Haifeng Du, Jinfeng Kang, Yu Ye
{"title":"Monolithic 3D Logic Gates Based on p-Te and n-Bi2S3 Complementary Thin-Film Transistors","authors":"Yuqia Ran, Yiwen Song, Long Li, Xujin Song, Pingfan Gu, Qi Wang, Haifeng Du, Jinfeng Kang, Yu Ye","doi":"10.1002/aelm.202400786","DOIUrl":"https://doi.org/10.1002/aelm.202400786","url":null,"abstract":"As Moore's law approaches its limit, achieving higher device density necessitates innovative architectures, with monolithic three-dimensional (M3D) designs emerging as a promising solution. Although numerous top-down fabrication methods have yielded encouraging results, they often fall short of meeting the demands for large-scale production, ultimately hindering the development of more complex, high-performance devices. Here, a novel approach employing all thermally evaporated thin films is presented for the bottom-up fabrication of M3D integrated logic circuits. Utilizing <i>p</i>-type tellurium (Te) and <i>n</i>-type bismuth sulfide (Bi<sub>2</sub>S<sub>3</sub>) as channel materials, monolithicly stacked prototypes of inverter, NAND, NOR, AND gates, SRAM, and oscillators are successfully demonstrated. This work highlights the viability of utilizing bottom-up synthesized thin-film transistors (TFTs) to construct sophisticated M3D logic circuits, underscoring the significance of deposition techniques such as thermal evaporation as a highly effective approach.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"33 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Photo-Thermal Approaches on Polyimide Film for Demonstration of Sub-50 µm Polymer Stencil Mask 在聚酰亚胺薄膜上采用光热方法演示 50 微米以下的聚合物模板掩模
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-01 DOI: 10.1002/aelm.202400979
Bon-Jae Koo, Jin-Hyeong Lee, Hyo-Kyung Kwon, Hwidon Lee, Joonsoo Jeong, Suk-Kyun Ahn, Min-Ho Seo
{"title":"Photo-Thermal Approaches on Polyimide Film for Demonstration of Sub-50 µm Polymer Stencil Mask","authors":"Bon-Jae Koo, Jin-Hyeong Lee, Hyo-Kyung Kwon, Hwidon Lee, Joonsoo Jeong, Suk-Kyun Ahn, Min-Ho Seo","doi":"10.1002/aelm.202400979","DOIUrl":"https://doi.org/10.1002/aelm.202400979","url":null,"abstract":"Stencil masks are widely utilized in traditional macro-scale patterning due to their simplicity and versatility in enabling various types of patterns. Compared to photoresist-based methods, stencil-based patterning enables chemical-free processing and curved surface application. However, their application to micro-scale patterning is constrained by challenges including precise fabrication, mechanical stability, and high production costs. Herein, a cost- and time-effective, single-step UV laser process is presented for fabricating polyimide stencil masks with micrometer-resolution (down to 42.4 µm feature sizes) by optimizing photothermal effects on material. Specifically, the processing conditions are systematically explored and optimized to enable efficient etching of polyimide with a UV laser while maintaining its structural stability in a glassy state. This approach successfully yielded micro-patterns with feature sizes below 50 µm on polyimide film. The developed method demonstrated high reproducibility, scalability, and stability, allowing polyimide films of varying thicknesses to be processed into stencil masks with dimensions down to 42.4 µm. Furthermore, the produced masks enable the formation of various micro-patterns, including polygonal shapes and linear features, with high aspect ratios (&lt;1:235.8) (42.4 µm width, 10 mm length). To demonstrate the practicality of this technology, wearable motion sensors are fabricated using stencil masks and successfully applied to advanced human-machine interaction.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"22 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical Model Development for Fabricating MIS-Anode-Based 1100 V AlGaN/GaN-Based Lateral Schottky Barrier Diodes Grown on Silicon Substrate with Low Leakage Current 用于制造在硅基底上生长的具有低漏泄电流的基于 MIS-Anode 的 1100 V AlGaN/GaN 侧肖特基势垒二极管的物理模型开发
IF 6.2 2区 材料科学
Advanced Electronic Materials Pub Date : 2025-04-01 DOI: 10.1002/aelm.202500111
Jingting He, Zhizhong Wang, Fuping Huang, Chunshuang Chu, Kangkai Tian, Shuting Cai, Yonghui Zhang, Xiaojuan Sun, Dabing Li, Xiaowei Sun, Zi-Hui Zhang
{"title":"Physical Model Development for Fabricating MIS-Anode-Based 1100 V AlGaN/GaN-Based Lateral Schottky Barrier Diodes Grown on Silicon Substrate with Low Leakage Current","authors":"Jingting He, Zhizhong Wang, Fuping Huang, Chunshuang Chu, Kangkai Tian, Shuting Cai, Yonghui Zhang, Xiaojuan Sun, Dabing Li, Xiaowei Sun, Zi-Hui Zhang","doi":"10.1002/aelm.202500111","DOIUrl":"https://doi.org/10.1002/aelm.202500111","url":null,"abstract":"This work develops unique physical models for AlGaN/GaN-based Schottky barrier diodes (SBDs) grown on silicon (Si) substrates. The carrier transport and impact ionization processes are different from those of devices grown on sapphire substrates. Defects in the GaN epitaxial layer generate abundant leakage current and the impact ionization coefficients for the GaN layer shall be revised. The revised physical models are utilized to design SBDs with metal/Al₂O₃/GaN-based (MIS) Schottky contact. Both numerically calculated and experimentally measured results prove the benefits of the passivation effect by the Al₂O₃ thin layer. The increased effective energy barrier height suppresses the image-force-caused energy band-lowering effect. As a result, the reverse leakage current is reduced by 3 orders of magnitude when compared with the reference SBD. The revised physical models predict a ≈1100 V breakdown voltage (<i>BV</i>) for the MIS SBD with a specific ON-resistance (<i>R</i><sub>on,sp</sub>) of ≈3.98 mΩ cm<sup>2</sup>, which numbers are consistent with measured results. The revised physical models are also able to precisely study the electrical stress reliability such that the MIS-based Schottky contact can significantly reduce the surface trapping effect for electrons. This is proven by experimentally observing that the MIS SBD presents much stabler <i>R</i><sub>on,sp</sub> and turn-on voltage (<i>V</i><sub>on</sub>) in different electrical-stress conditions.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"73 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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