Advanced Electronic Materials最新文献

{"title":"Dual-Layer-Per-Array Operation Using Local Polarization Switching of Ferroelectric Tunnel FETs for Massive Neural Networks (Adv. Electron. Mater. 4/2025)","authors":"Jae Seung Woo,&nbsp;Chae Lin Jung,&nbsp;Jin Ho Chang,&nbsp;Minjeong Ryu,&nbsp;Woo Young Choi","doi":"10.1002/aelm.202570011","DOIUrl":"https://doi.org/10.1002/aelm.202570011","url":null,"abstract":"<p><b>Dual-Layer-Per-Array Operations</b></p><p>In article number 2400606, Woo Young Choi and co-workers propose and implement a novel dual-layer-per-array operation in a FeTFET array for large-scale neural network implementations. Owing to independently controllable two current regions, dual-layer vector-matrix multiplication operations can be performed within a single FeTFET synapse array, enabling identical neural network implementation in half the area of the conventional neuromorphic hardware.\u0000\u0000 <figure>\u0000 <div><picture>\u0000 <source></source></picture><p></p>\u0000 </div>\u0000 </figure></p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 4","pages":""},"PeriodicalIF":5.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202570011","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor","authors":"Kiyung Kim, Minjae Kim, Yongsu Lee, Hae-Won Lee, Jae Hyeon Jun, Jun-Hyeok Choi, Seongbeen Yoon, Hyeon-Jun Hwang, Byoung Hun Lee","doi":"10.1002/aelm.202500031","DOIUrl":"https://doi.org/10.1002/aelm.202500031","url":null,"abstract":"The complementary field-effect transistor (CFET) structure is a highly area-efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recrystallization, which has been limiting further development. In this paper, an alternative method is proposed to realize CFETs using p-type tellurium (Te) (for the lower-level channel) and n-type zinc oxide (ZnO) (for the upper-level channel). Te and ZnO are directly deposited on a 30 × 30 mm² SiO₂/Silicon substrate, using a considerably low-temperature fabrication process (&lt;150 °C). The lower p-type channel exhibits superior mobility exceeding 10 cm² V⁻¹ s⁻¹ even after the integration of the entire CFET process. The CFET inverter demonstrates a voltage gain &gt;51 at <i>V</i>_DD = 4 V and noise margins of 0.36 and 0.45 V at <i>V</i>_DD = 1 V. Using the same integration process, functional NAND and NOR logic gates are successfully demonstrated in the vertically integrated CFET structure. The proposed ZnO/Te CFET can be a promising device technology, particularly for 3D and heterojunction integration requiring a low thermal budget.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"23 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143767139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solution-Shearing of Highly Smooth Ion-Gel Thin Films: Facilitating the Deposition of Organic Semiconductors for Ion-Gated Organic Field Effect Transistors","authors":"Jonathan Perez Andrade,&nbsp;Angelika Wrzesińska-Lashkova,&nbsp;Anupam Prasoon,&nbsp;Felix Talnack,&nbsp;Katherina Haase,&nbsp;Bernd Büchner,&nbsp;Xinliang Feng,&nbsp;Yana Vaynzof,&nbsp;Mike Hambsch,&nbsp;Yulia Krupskaya,&nbsp;Stefan C. B. Mannsfeld","doi":"10.1002/aelm.202400312","DOIUrl":"10.1002/aelm.202400312","url":null,"abstract":"<p>A straightforward method is developed to produce ion-gels (IGs) with surface roughness at the nanometer level using a solution-shearing process, enabling the first successful growth of crystalline, small-molecule organic semiconductor (OSC) films directly on the IG layer. The effectiveness of this approach is demonstrated by fabricating top-contact electrolyte-gated organic field-effect transistors (EGOFETs) using thermal vapor deposition and solution-shearing. The gel matrix consists of polymethyl methacrylate (PMMA) or its blend with poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF:HFP), and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]) serves as ionic liquid. X-ray photoemission spectroscopy (XPS) reveals that the shearing speed controls the  polymer phase separation in the blended gels, producing capacitance values of up to 10.1 µF cm⁻². The exceptional smoothness of the gel films permits vacuum deposition polycrystalline films of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophen (C8-BTBT), dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophen (DNTT), and 2,9-didecyldinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C10-DNTT), and solution-shearing of C8-BTBT and 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) on their surfaces. Grazing incidence wide-angle X-ray scattering (GIWAXS) can now be conducted directly on the OSC films without obstruction by the gel. EGOFETs with minimal hysteresis and mobilities up to 1.46 cm² V⁻¹ s⁻¹ are obtained for C10-DNTT. This study underscores the possibility of producing transistor-grade polycrystalline organic semiconductor films on top of IGs, making them attractive for surface characterization techniques and in situ measurements.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 6","pages":""},"PeriodicalIF":5.3,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202400312","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143776052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monolithic 3D Logic Gates Based on p-Te and n-Bi2S3 Complementary Thin-Film Transistors","authors":"Yuqia Ran, Yiwen Song, Long Li, Xujin Song, Pingfan Gu, Qi Wang, Haifeng Du, Jinfeng Kang, Yu Ye","doi":"10.1002/aelm.202400786","DOIUrl":"https://doi.org/10.1002/aelm.202400786","url":null,"abstract":"As Moore's law approaches its limit, achieving higher device density necessitates innovative architectures, with monolithic three-dimensional (M3D) designs emerging as a promising solution. Although numerous top-down fabrication methods have yielded encouraging results, they often fall short of meeting the demands for large-scale production, ultimately hindering the development of more complex, high-performance devices. Here, a novel approach employing all thermally evaporated thin films is presented for the bottom-up fabrication of M3D integrated logic circuits. Utilizing <i>p</i>-type tellurium (Te) and <i>n</i>-type bismuth sulfide (Bi₂S₃) as channel materials, monolithicly stacked prototypes of inverter, NAND, NOR, AND gates, SRAM, and oscillators are successfully demonstrated. This work highlights the viability of utilizing bottom-up synthesized thin-film transistors (TFTs) to construct sophisticated M3D logic circuits, underscoring the significance of deposition techniques such as thermal evaporation as a highly effective approach.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"33 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Photo-Thermal Approaches on Polyimide Film for Demonstration of Sub-50 µm Polymer Stencil Mask","authors":"Bon-Jae Koo, Jin-Hyeong Lee, Hyo-Kyung Kwon, Hwidon Lee, Joonsoo Jeong, Suk-Kyun Ahn, Min-Ho Seo","doi":"10.1002/aelm.202400979","DOIUrl":"https://doi.org/10.1002/aelm.202400979","url":null,"abstract":"Stencil masks are widely utilized in traditional macro-scale patterning due to their simplicity and versatility in enabling various types of patterns. Compared to photoresist-based methods, stencil-based patterning enables chemical-free processing and curved surface application. However, their application to micro-scale patterning is constrained by challenges including precise fabrication, mechanical stability, and high production costs. Herein, a cost- and time-effective, single-step UV laser process is presented for fabricating polyimide stencil masks with micrometer-resolution (down to 42.4 µm feature sizes) by optimizing photothermal effects on material. Specifically, the processing conditions are systematically explored and optimized to enable efficient etching of polyimide with a UV laser while maintaining its structural stability in a glassy state. This approach successfully yielded micro-patterns with feature sizes below 50 µm on polyimide film. The developed method demonstrated high reproducibility, scalability, and stability, allowing polyimide films of varying thicknesses to be processed into stencil masks with dimensions down to 42.4 µm. Furthermore, the produced masks enable the formation of various micro-patterns, including polygonal shapes and linear features, with high aspect ratios (&lt;1:235.8) (42.4 µm width, 10 mm length). To demonstrate the practicality of this technology, wearable motion sensors are fabricated using stencil masks and successfully applied to advanced human-machine interaction.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"22 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical Model Development for Fabricating MIS-Anode-Based 1100 V AlGaN/GaN-Based Lateral Schottky Barrier Diodes Grown on Silicon Substrate with Low Leakage Current","authors":"Jingting He, Zhizhong Wang, Fuping Huang, Chunshuang Chu, Kangkai Tian, Shuting Cai, Yonghui Zhang, Xiaojuan Sun, Dabing Li, Xiaowei Sun, Zi-Hui Zhang","doi":"10.1002/aelm.202500111","DOIUrl":"https://doi.org/10.1002/aelm.202500111","url":null,"abstract":"This work develops unique physical models for AlGaN/GaN-based Schottky barrier diodes (SBDs) grown on silicon (Si) substrates. The carrier transport and impact ionization processes are different from those of devices grown on sapphire substrates. Defects in the GaN epitaxial layer generate abundant leakage current and the impact ionization coefficients for the GaN layer shall be revised. The revised physical models are utilized to design SBDs with metal/Al₂O₃/GaN-based (MIS) Schottky contact. Both numerically calculated and experimentally measured results prove the benefits of the passivation effect by the Al₂O₃ thin layer. The increased effective energy barrier height suppresses the image-force-caused energy band-lowering effect. As a result, the reverse leakage current is reduced by 3 orders of magnitude when compared with the reference SBD. The revised physical models predict a ≈1100 V breakdown voltage (<i>BV</i>) for the MIS SBD with a specific ON-resistance (<i>R</i>_on,sp) of ≈3.98 mΩ cm², which numbers are consistent with measured results. The revised physical models are also able to precisely study the electrical stress reliability such that the MIS-based Schottky contact can significantly reduce the surface trapping effect for electrons. This is proven by experimentally observing that the MIS SBD presents much stabler <i>R</i>_on,sp and turn-on voltage (<i>V</i>_on) in different electrical-stress conditions.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"73 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Mobility p-Channel Thin-Film Transistors Based on Polycrystalline GeSn","authors":"Kenta Moto, Shintaro Maeda, Kota Igura, Linyu Huang, Atsuki Morimoto, Keisuke Yamamoto, Kaoru Toko","doi":"10.1002/aelm.202400901","DOIUrl":"https://doi.org/10.1002/aelm.202400901","url":null,"abstract":"GeSn has gained significant interest as a material for next-generation electronic devices, including thin-film transistors (TFTs) because of its excellent electronic properties. In this study, high-quality polycrystalline GeSn thin films are fabricated on glass substrates and fabricated high-performance TFTs. A bilayer structure with modulated deposition temperatures simultaneously suppressed nucleation and promoted growth, thereby enabling the formation of large-grained GeSn layers. The sample exhibited high Hall hole mobility (230 cm² V⁻¹ s⁻¹) and low hole concentration (4.1 × 10¹⁷ cm⁻³), which are the best electrical properties for polycrystalline Ge-based thin films applicable for accumulation-mode TFTs. The fabricated TFTs demonstrated field-effect mobility of up to 250 cm² V⁻¹ s⁻¹. This value is not only the highest for a polycrystalline Ge-based TFT, but also the highest for a p-channel TFT fabricated in a low-temperature process (≤500 °C). Thus, this study represents an important step toward the realization of high-performance TFTs using GeSn, which is a significant achievement that can contribute to the next generation of electronics technologies.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"52 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143758368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-Channel, Amorphous Oxide Thin-Film Transistor Exhibiting High Mobility of 67 cm2 V−1 s−1 and Excellent Stability","authors":"Mohammad Masum Billah, Md Mobaidul Islam, Sunaina Priyadarshi, Jung Bae Kim, Yang Ho Bae, Rodney Lim, Dejiu Fan, Zero Hung, Dong Kil Yim, Soo Yong Choi, Youron Lin, Juergen Grillmayer, Custer Ma, Lynn Yang, Julian Chen, Jin Jang","doi":"10.1002/aelm.202400766","DOIUrl":"https://doi.org/10.1002/aelm.202400766","url":null,"abstract":"Multi-channel amorphous oxide thin-film transistors (TFTs) with dual gate (DG), coplanar structure are studied. The multi-channel consists of a top amorphous indium gallium zinc tin oxide (a-IGZTO) and a very thin amorphous indium zinc oxide (a-IZO) bottom layer. The fabricated TFTs exhibit high field-effect mobility (µ_FE) ≈67.1 cm² V⁻¹ s⁻¹, and excellent stability under positive bias temperature stress (PBTS). The band diagram of the multi-channel TFT is presented based on UV photoelectron spectroscopy, X-ray photoelectron spectroscopy, and UV–vis spectroscopy measurements. The PBTS robustness is interpreted as the formation of 2D electron gas (2DEG) at the a-IGZTO/a-IZO hetero-interface which extends to the bulk a-IZO layer. From thermalization energy (E_Th) analysis with the energy barrier to defect formation under PBTS, the multi-channel TFT exhibits the largest E_Th of 0.84 eV, which indicates that more stress energy is needed for threshold voltage shift during PBTS in the TFTs as compared to single-channel TFTs.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"73 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Al/Ti Electrodes on the Performance and Operational Stability of n-Channel Solution-Processed Solid-State Electrolyte-Gated Transistors: Applications in Reservoir Computing","authors":"Quanhua Chen, Xiang Wan, Walid Boukhili, Jie Yan, Hong Zhu, Lijian Chen, Chee Leong Tan, Zhihao Yu, Huabin Sun, Yong Xu, Dongyoon Khim","doi":"10.1002/aelm.202500038","DOIUrl":"https://doi.org/10.1002/aelm.202500038","url":null,"abstract":"The impact of Al/Ti electrodes on enhancing the performance and operational stability of n-channel organic electrolyte-gated transistors (OEGTs) is investigated. Utilizing Al/Ti electrodes as source and drain electrodes in diketopyrrolopyrrole (DPP)-based polymeric semiconductor OEGTs leads to a significant decrease in the charge injection barrier for electrons, resulting in improvement of all electrical parameters including on-current, mobility, on-off ratio, and threshold voltages. Furthermore, through a comparative analysis of transistors utilizing polymer insulators and solid electrolytes as gate dielectrics, the effect of alterations in the electrodes on the contact resistance of each device is examined. In comparison to OEGTs with Au electrodes, OEGTs with Al/Ti electrodes demonstrate higher operational stability following multiple cycling tests. Finally, the OEGTs produced in this study demonstrate reliable short-term memory characteristics, which are subsequently utilized for reservoir computing, achieving a high recognition accuracy of 94% for spoken digits.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"36 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward an Internet of Things Circular Economy Using Printed Circuits on Reusable Steel Substrates","authors":"Jeff Kettle,&nbsp;Rudra Mukherjee,&nbsp;Shoushou Zhang,&nbsp;Tianwei Zhang,&nbsp;Jonathan Harwell,&nbsp;Andrew Bainbridge,&nbsp;Mahmoud Wagih,&nbsp;Ana Martinez Diez,&nbsp;MariFe Menendez Suarez,&nbsp;Pascal Sanchez","doi":"10.1002/aelm.202400529","DOIUrl":"10.1002/aelm.202400529","url":null,"abstract":"<p>There is a pressing need to reduce electronic waste, which along with government edicts and national time-bound policy directives are shaping the drive toward circular economy solutions in electronics. However, there is no industrially standardized approach for fabricating high-throughput recyclable and reusable electronic assemblies. Herein, we present the functionalization of steel over large areas with low-cost insulative intermediate layers as Printed Circuit Boards (PCBs), enabling an electronics circular economy. Roll-to-roll-friendly reusable steel substrates are coated using Sol–gel-based low-roughness insulative layers, with conductive tracks and solder pads additively manufactured with direct-write printing. To demonstrate how degradable 3D scaffolds could enable wireless applications, RF components, and wi-fi nodes are demonstrated with 3D-printed antennas showing the feasibility of broadband Internet of Things applications up to 6 GHz. At their end-of-life, the steel-based PCBs are sonicated in non-hazardous solvents allowing for the rapid recovery of components and precious metals. The environmental benefits of our approach are discussed using Life Cycle Assessments (LCA) and a comparative LCA between these scenarios has been undertaken. Consideration of the final product cost is given and potential business models to enter the electronics market are identified.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 5","pages":""},"PeriodicalIF":5.3,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202400529","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}