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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献

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On accumulator-based bit-serial test response compaction schemes 基于累加器的位串行测试响应压缩方案
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915255
D. Bakalis, D. Nikolos, H. T. Vergos, X. Kavousianos
{"title":"On accumulator-based bit-serial test response compaction schemes","authors":"D. Bakalis, D. Nikolos, H. T. Vergos, X. Kavousianos","doi":"10.1109/ISQED.2001.915255","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915255","url":null,"abstract":"The data paths of most contemporary general and special purpose processors include registers, adders and other arithmetic circuits. If these circuits are also used for built-in self-test, the extra area required for embedding testing structures can be cut down efficiently. Several schemes based on accumulators, subtracters, multipliers and shift, resisters have been proposed and analyzed in the past for parallel test response compaction, whereas some efforts have also been devoted in the bit-serial response compaction case. In this paper, we analyse and evaluate the bit-serial version of a recently proposed scheme for parallel test response compaction. Experimental results on the ISCAS'85 benchmark circuits indicate that the post-compaction fault coverage drop attained by the new scheme is significantly lower than other already known accumulator-based compaction schemes.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process 在0.25-/spl mu/m浅沟隔离硅化体CMOS工艺中，紧凑的布局规则提取用于锁止预防
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915241
M. Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang
{"title":"Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process","authors":"M. Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang","doi":"10.1109/ISQED.2001.915241","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915241","url":null,"abstract":"An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS ICs is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-/spl mu/m shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS ICs, but still to maintain high enough latchup immunity in bulk CMOS ICs.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126306461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A "design for verification" methodology “为验证而设计”的方法
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915205
F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi
{"title":"A \"design for verification\" methodology","authors":"F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi","doi":"10.1109/ISQED.2001.915205","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915205","url":null,"abstract":"New tools are becoming available on the market that help alleviate the problem and improve the quality of functional verification of today's complex systems. A methodology that makes use of such tools is described and compared to the traditional approach followed in the context of a specific project. The scope is limited to functional verification but spans from block- to system level.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130088117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Color counting and its application to path delay fault coverage 颜色计数及其在路径延迟故障覆盖中的应用
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915259
J. Deodhar, S. Tragoudas
{"title":"Color counting and its application to path delay fault coverage","authors":"J. Deodhar, S. Tragoudas","doi":"10.1109/ISQED.2001.915259","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915259","url":null,"abstract":"We propose a new technique for computing exact fault coverage for any fault model. It consists of appropriate formation and counting of colors. Each color represents a set of faults, and the definition of colors varies according to the fault model. The technique utilizes the two aspects on which the fault coverage for any model depends, the circuit lines and the patterns applied to the circuit. Depending upon the sample space of faults for a given model, the representation of faults as colors differs. Colors are generated in a greedy and on demand manner ensuring they are unique. Even though the technique is simple in nature, it has never been used to calculate fault coverage for any fault model before. In this paper we apply it to calculate the fault coverage for the path delay fault model. Our experimental results show improvement over the existent techniques for the above mentioned model.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134551197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Instruction prediction for step power reduction 步进功率降低的指令预测
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915229
Zhenyu Tang, Lei He, N. Chang, Shen Lin, Weize Xie, O. S. Nakagawa
{"title":"Instruction prediction for step power reduction","authors":"Zhenyu Tang, Lei He, N. Chang, Shen Lin, Weize Xie, O. S. Nakagawa","doi":"10.1109/ISQED.2001.915229","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915229","url":null,"abstract":"Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more concerned with the step power reduction instead of the average power reduction. The step power is defined as the power difference between the previous and present clock cycles, and represents the Ldi/dt noise at the microarchitecture level. Two mechanisms at the microarchitecture level are proposed in this paper to reduce the step power of the floating point unit (FPU), as FPU is the potential \"hot\" spot of Ldi/dt noise. The two mechanisms, ramping up and ramping down FPU based on instruction fetch queue (IFQ) scanning and PC+N instruction diction, can meet any specific step power constraint. We implement and evaluate the two mechanisms using a performance and power simulator based on the SimpleScalar toolset. Experiments using SPEC95 benchmarks show that our method reduces the performance loss by a factor of four when compared to a recent work.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124988445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os 带有外设I/O的asic的I/O单元放置和电气检查方法
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915208
Gulsun Yasar, Charles Chiu, R. Proctor, J. Libous
{"title":"I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os","authors":"Gulsun Yasar, Charles Chiu, R. Proctor, J. Libous","doi":"10.1109/ISQED.2001.915208","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915208","url":null,"abstract":"Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121321887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Early detection of design sensitivities that cause yield loss for new products 尽早发现导致新产品良率损失的设计敏感性
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915266
R. Ross, Keith McCasland
{"title":"Early detection of design sensitivities that cause yield loss for new products","authors":"R. Ross, Keith McCasland","doi":"10.1109/ISQED.2001.915266","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915266","url":null,"abstract":"This paper describes an analytical method for detecting IC design sensitivities that adversely, affect wafer probe yields. The same method can also detect systematic process problems that affect probe yields. The method not only detects these sensitivities, but also can give valuable information about why the probe yield is affected. Also, quantitative yield limits can be calculated for each sensitivity thus making it possible to create a yield loss Pareto and concentrate yield improvement efforts on those sensitivities causing the greatest loss. This method has proven to be accurate and reliable when performed on data from significantly fewer wafers than might be required for other techniques. An automated computer program has been developed by the authors to perform the analysis.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131398026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory hierarchy optimization of multimedia applications on programmable embedded cores 可编程嵌入式核上多媒体应用的内存层次优化
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915271
K. Tatas, A. Argyriou, M. Dasygenis, D. Soudris, N. Zervas
{"title":"Memory hierarchy optimization of multimedia applications on programmable embedded cores","authors":"K. Tatas, A. Argyriou, M. Dasygenis, D. Soudris, N. Zervas","doi":"10.1109/ISQED.2001.915271","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915271","url":null,"abstract":"Data memory hierarchy optimization and partitioning for a widely used multimedia application kernel known as the hierarchical motion estimation algorithm is undertaken, with the use of global loop and data-reuse transformations for three different embedded processor architecture models. Exhaustive exploration of the obtained results clarifies the effect of the transformations on power, area, and performance and also indicates a relation between the complexity of the application and the power savings obtained by this strategy. Furthermore, the significant contribution of the instruction memory even after the application of performance optimizations to the total power budget becomes evident and a methodology is introduced in order to reduce this component.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124266666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
One approach to analog system design problem formulation 模拟系统设计问题表述的一种方法
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915242
A. Zemliak
{"title":"One approach to analog system design problem formulation","authors":"A. Zemliak","doi":"10.1109/ISQED.2001.915242","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915242","url":null,"abstract":"The formulation of the process of analog system design has been done on the basis of the control theory application. This approach generalizes the design process and produces many different design trajectories inside the same optimization procedure. The problem of the optimal design algorithm construction is defined as the minimal time problem of the control theory. This idea was tested with different optimization procedures. Numerical results of some simple electronic circuit designs demonstrate the efficiency of the proposed approach. These examples show that the traditional design strategy is not time-optimal and the computer time gain of the optimal design strategy with respect to the traditional design strategy increases when the size and complexity of the system increase.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Impact of on-chip inductance when transitioning from Al to Cu based technology 从铝基技术过渡到铜基技术时片上电感的影响
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915223
Tom Chen
{"title":"Impact of on-chip inductance when transitioning from Al to Cu based technology","authors":"Tom Chen","doi":"10.1109/ISQED.2001.915223","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915223","url":null,"abstract":"How does on-chip inductance impact timing closure when transitioning from Al to Cu based technology? This paper presents some experimental results based on a Al-based 0.18 /spl mu/m CMOS process and a Cu-based 0.13 /spl mu/m CMOS process. The results show that the impact of on-chip inductance is slightly more on the Cu-based 0.13 /spl mu/m process than on the Al-based 0.18 /spl mu/m process. Furthermore, the results demonstrate that on-chip inductance plays an insignificant role if we assume a perfect power supply network around the interconnect routes.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123526276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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