{"title":"An effective current source cell model for VDSM delay calculation","authors":"A. Korshak, Jyh-Chwen Lee","doi":"10.1109/ISQED.2001.915246","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915246","url":null,"abstract":"We present a new approach to model delay of the digital cell in very deep submicron (VDSM) IC designs. It provides higher accuracy for both delay and transition time than the conventional effective capacitance approximation. The cell is modeled by an effective current source that emulate the behavior of the transistor network. The proposed model is based upon the standard timing tables of the characterized cell.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"9 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120999786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Defect-oriented fault simulation and test generation in digital circuits","authors":"W. Kuzmicz, W. Pleskacz, J. Raik, R. Ubar","doi":"10.1109/ISQED.2001.915257","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915257","url":null,"abstract":"A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows one to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for higher level fault simulation purposes. In such a way, the functional fault model can be regarded as an interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows one to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCAS'85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to a considerable overestimation of the result.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127073209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Foundry's perspective of system integration: quality design and time-to-volume","authors":"Sheldon Wu, F. Wang, Lie-Szu Juang","doi":"10.1109/ISQED.2001.915214","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915214","url":null,"abstract":"Component development with complicated system integration faces great new challenges in today's disintegrated IC industry. Designers have to collaborate with different vendors of EDA tools, design flows, library, IP, and manufacturing process globally who all have different views of quality and deliverability. The purpose of this paper is to demonstrate how a foundry can support the design community by setting up standards and methodologies from process technology development to design infrastructure development. Using the integrated services with common roots, designers can enjoy the highest quality and best time-to-volume for system integration.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133987160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computational cost reduction in extracting inductance","authors":"Y. Nakashima, M. Ikeda, K. Asada","doi":"10.1109/ISQED.2001.915224","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915224","url":null,"abstract":"Until now, the miniaturization by scaling law has developed the technology of VLSI circuits. With this miniaturization much faster speed and much better performance circuits have been obtained. This miniaturization is expected to continue and the clock speed will become much faster than now, which means that we have to encounter a problem that is caused by inductance. In these background there are a lot of papers in extracting inductance. At the same time calculating inductance is considered very tiresome task because it needs a lot of computational cost of that. In this paper we introduce new ideas and new methods to reduce computational cost of calculating inductance. We have developed a frequency dependent inductance calculation simulator for cost reduction of calculating inductance and found that the results of the simulator had a good agreement with those of the conventional methods. With this simulator we also show some effects of inductance in circuit behavior.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125423574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Noise in radio frequency circuits: analysis and design implications","authors":"A. Mehrotra","doi":"10.1109/ISQED.2001.915273","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915273","url":null,"abstract":"This paper provides an overview of noise analysis techniques and noise models for radio frequency (RF) circuits and the implication of noise constraints on RF circuit design. In order to accurately account for the circuit nonlinearities, the circuit noise sources are modelled as stochastic processes and the circuit equations are solved with these stochastic processes as inputs, using techniques from stochastic calculus. Noise analysis and modelling techniques are presented for both autonomous (oscillatory) and non-autonomous circuits. Using these models, noise analysis of a phase feedback system (phase-locked loop) is also presented. Additionally, design techniques for minimizing noise in these circuits which are based on these analyses are also presented.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Constructive floorplanning with a yield objective","authors":"R. Prasad, I. Koren","doi":"10.1109/ISQED.2001.915240","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915240","url":null,"abstract":"The ability to improve the yield of integrated circuits through layout modification has been recognized, and several techniques for yield enhanced routing and compaction have been developed. Still, yield issues are rarely a factor in the choice of the floorplan mainly due to the tendency to focus on the more important timing and area objectives. Consequently, floorplanning tools have been developed with only these primary objectives in mind. We show in this paper that it is possible to generate a better floorplan with respect to yield with very little penalty in the main objectives. We describe a constructive floorplanning approach which is based on analytical techniques and produces near optimal floorplans in terms of area utilization, wiring length and yield.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis and design of ESD protection circuits for high-frequency/RF applications","authors":"C. Ito, K. Banerjee, R. Dutton","doi":"10.1109/ISQED.2001.915215","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915215","url":null,"abstract":"Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high frequency and RF circuits. This work presents for the first time, an S-parameter based analysis of the performance of RF circuits with various ESD protection designs. Additionally, a design methodology for distributed ESD protection using coplanar waveguides is developed to achieve a better impedance match over a broad frequency range. By using this technique, an ESD device with a parasitic capacitance of 200 fF will attenuate the signal power by only 0.27 dB at 10 GHz.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127800014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New efficient and accurate moment matching based model for crosstalk estimation in coupled RC trees","authors":"Qingjian Yu, E. Kuh","doi":"10.1109/ISQED.2001.915220","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915220","url":null,"abstract":"In this paper we provide a new efficient moment matching based model for the estimation of crosstalk in coupled RC tree networks. This model is formulated based on an exact and efficient linear order recursive algorithm for the moment computation of such networks with both lumped and distributed RC elements. The formulas used in the model are efficiently obtained by using the results of moment computation without any matrix operation and can fit for arbitrary input waveforms. Simulation results show it performs better than all existing formulas.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134378828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ATPG for path delay faults without path enumeration","authors":"M. Michael, S. Tragoudas","doi":"10.1109/ISQED.2001.915260","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915260","url":null,"abstract":"We present a new ATPG methodology for detecting path delay faults in combinational circuits. The proposed approach is non-enumerative and generates a small number of test patterns with high fault coverage. A new ATPG framework for path delay faults is introduced; it collapses the two phases (path sensitization and line justification) of traditional ATPGs into one. The proposed framework utilizes both structural and functional techniques. A BDD-based implementation and experimentation with the ISCAS'85 benchmarks shows that the proposed method outperforms all ATPG methods that bound the test set. The results also show that the approach is comparable to existing ATPG methods that do not bound the test set.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Refinements of Rent's rule allowing accurate interconnect complexity modeling","authors":"P. Verplaetse","doi":"10.1109/ISQED.2001.915235","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915235","url":null,"abstract":"The complexity of the interconnect topology of a circuit is well captured by Rent's rule. This rule can be applied for a priori wire-length estimation, which is useful for improving the quality of generated layouts, and could be used for reducing the number of design iterations. It can also successfully be applied for the generation of synthetic benchmark circuits. However Rent's role is an empirical approximation, and there are many deviations. This paper describes possible extensions to Rent's rule and discusses some of its applications.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126641829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}