Constructive floorplanning with a yield objective

Abstract

The ability to improve the yield of integrated circuits through layout modification has been recognized, and several techniques for yield enhanced routing and compaction have been developed. Still, yield issues are rarely a factor in the choice of the floorplan mainly due to the tendency to focus on the more important timing and area objectives. Consequently, floorplanning tools have been developed with only these primary objectives in mind. We show in this paper that it is possible to generate a better floorplan with respect to yield with very little penalty in the main objectives. We describe a constructive floorplanning approach which is based on analytical techniques and produces near optimal floorplans in terms of area utilization, wiring length and yield.