Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献

Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion 多信号线的有效片上电感建模及其在中继器插入中的应用

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2002-12-01 DOI: 10.1109/ISQED.2001.915225

Yu Cao, Xuejue Huang, N. Chang, Shen Lin, O. S. Nakagawa, Weize Xie, D. Sylvester, C. Hu

引用次数: 49

A method of embedded memory access time measurement 一种嵌入式存储器访问时间测量方法

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-28 DOI: 10.1109/ISQED.2001.915272

Nai-Yin Sung, Tsung-Yi Wu

引用次数: 9

An evaluation of single-ended and differential impedance in PCBs pcb中单端阻抗和差分阻抗的评估

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-28 DOI: 10.1109/ISQED.2001.915247

M. Mechaik

{"title":"An evaluation of single-ended and differential impedance in PCBs","authors":"M. Mechaik","doi":"10.1109/ISQED.2001.915247","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915247","url":null,"abstract":"The electrical performance of pulses propagating in Printed Circuit Boards (PCBs) is determined by the characteristic impedance, differential impedance, and terminating impedance of both single-ended and differential pairs. In this paper, numerical values are evaluated for the characteristic impedance, differential impedance, and common mode impedance of microstrip and strip transmission lines embedded in a PCB stack up. These numerical values are also plotted for different values of frequency, ratios of signal width to signal height above a ground plane, and signal separation to signal height. Even and differential mode impedances are also evaluated and plotted for two common termination circuits used in routing peripheral connect interface bus (PCI), point-to-point low voltage differential signaling (LVDS), or multipoint to multipoint differential signaling bus (LVDSM). It is also shown that appropriate values of RC termination filters can be used effectively to match common mode and differential mode impedances thereby reducing EMC emissions, minimizing reflections, and providing stable differential input voltage swing levels. The plots aid in the design of differential signalling and controlled layer impedance.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121725207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Hot-carrier-induced circuit degradation for 0.18 /spl mu/m CMOS technology 0.18 /spl mu/m CMOS技术的热载流子诱导电路退化

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-28 DOI: 10.1109/ISQED.2001.915244

Wei Li, Qiang Li, J. Yuan, J. McConkey, Yuan Chen, S. Chetlur, Jonathan Zhou, A. Oates

引用次数: 7

Signal attenuation in transmission lines 传输线中的信号衰减

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-28 DOI: 10.1109/ISQED.2001.915226

M. Mechaik

引用次数: 12

Scaling-induced reductions in CMOS reliability margins and the escalating need for increased design-in reliability efforts 规模导致CMOS可靠性裕度降低，对可靠性设计工作的需求不断增加

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-28 DOI: 10.1109/ISQED.2001.915216

J. McPherson

引用次数: 27

Memory bus encoding for low power: a tutorial 低功耗存储器总线编码:教程

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-28 DOI: 10.1109/ISQED.2001.915227

W. Cheng, Massoud Pedram

引用次数: 43

Stopping criteria comparison: towards high quality behavioral verification 停止标准比较:走向高质量的行为验证

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915202

A. Hajjar, Tom Chen, Isabelle Munn, A. Andrews, M. Bjorkman

引用次数: 5

Trading bitwidth for array size: a unified reconfigurable arithmetic processor design 为数组大小交易位宽:一个统一的可重构算术处理器设计

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915251

R. Lin

{"title":"Trading bitwidth for array size: a unified reconfigurable arithmetic processor design","authors":"R. Lin","doi":"10.1109/ISQED.2001.915251","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915251","url":null,"abstract":"This paper presents a novel unified run-time reconfigurable arithmetic processor design scheme. It provides novel computational trade-offs between array/matrix size and input data item bitwidth, and efficiently performs multiple types of arithmetic operations in pipeline within a single hardware-reusable processor. The proposed computations include inner product evaluation, matrix multiplication, and evaluation of polynomial. More specifically, we show that the minimum hardware platform can be easily reconfigured to complete: [1] the inner products of two input arrays with several combinations of array dimension and precision, including input arrays of 256 4-bit items, 64 8-bit items, 16 16-bit items, 4 32-bit items and I 64-bit item; (2) the product of matrices X/sub nk/ and Y/sub km/ for any integers n, k, m and any item precision b ranging from 4 to 64 bits, including input arrays of X/sub 16/spl times/16/ Y/sub 16/spl times/16/ of 4-bit items, X/sub 8/spl times/8/ and Y/sub 8/spl times/8/ of 8-bit items, X/sub 4/spl times/4/, Y/sub 4/spl times/4/ of 16-bit items, X/sub 2/spl times/2/ and Y/sub 2/spl times/2/ of 32-bit items and the product of two 64-bit numbers; (3) the polynomial evaluations at any given point x, with several combinations of the polynomial degree N and evaluation point number precision p, including polynomial degree and item precision options of N=64, p=13, N=16, p=16, and N=4, p=32.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129412932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Techniques that improved the timing convergence of the Gekko PowerPC microprocessor 改进Gekko PowerPC微处理器时序收敛的技术

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915207

P. Kartschoke, S. Hojat

引用次数: 2