Hot-carrier-induced circuit degradation for 0.18 /spl mu/m CMOS technology

Abstract

Because the supply voltage is not proportionally scaled with the device size, the further scaling down of CMOS devices is in turn accompanied with more and more severe hot-carrier reliability problems. Hot-carriers, the high energy carriers due to high electric field in the channel, are injected into the gate oxide or cause trapping states generation between Si and SiO/sub 2/ interface, which is accumulated and causes long run reliability problems in devices and circuits. In this paper, we describe a systematic method to evaluate the circuit degradation due to hot-carrier stressing. First the substrate current and gate leakage current models are improved for more accuracy in predicting the lifetime of the devices and circuits. The hot-carrier stressing characterization is carried out for 0.18 /spl mu/m technology. The circuit performance degradation is then evaluated using the parameters extracted from 0.18 /spl mu/m technology for both digital logic circuits and RF circuits.