Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献_第2页

Implementation of multipliers in FPGA structures FPGA结构中乘法器的实现

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915265

K. Wiatr, E. Jamro

引用次数: 27

High quality analog CMOS and mixed signal LSI design 高品质模拟CMOS和混合信号LSI设计

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915212

A. Matsuzawa

{"title":"High quality analog CMOS and mixed signal LSI design","authors":"A. Matsuzawa","doi":"10.1109/ISQED.2001.915212","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915212","url":null,"abstract":"This paper presents an overview of high quality design methodology both in the analog CMOS and in the mixed signal LSI. The important design considerations in analog CMOS are first discussed. Not only taking the conventional methodology into account but also taking care of the process fluctuation, including V/sub T/ mismatch or 1/f noise, leading to robust and high quality analog CMOS circuits. For the rapid-growing high frequency applications, parasitic effects such as cross-coupled capacitance and substrate power loss are becoming serious issues. Thus it is demonstrated that pre- and post-layout simulations are vital to achieve target characteristics. The mixed signal LSI design today requires system-level simulation in order to meet the competitive performance specifications. The mixed-mode simulation, using SPICE, Verlog-D, and Verilog-A, which can concurrently handle analog and digital circuits, is shown to be essential to the overall mixed signal system design. The substrate noise or EMI need to be analyzed effectively under such an environment as well. Finally, accurate device parameter extraction, its careful reflection to above circuit designs, and fine parameter control in manufacturing for the active and passive devices are described.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Power grid modeling technique for hierarchical power network analysis 分层电网分析的电网建模技术

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915249

N. Zhu, Han Young Koh

引用次数: 2

ELITE design methodology of foundation IP for improving synthesis quality 提高合成质量的基础IP ELITE设计方法

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915263

Chih-Yuan Chen, S. Tung

{"title":"ELITE design methodology of foundation IP for improving synthesis quality","authors":"Chih-Yuan Chen, S. Tung","doi":"10.1109/ISQED.2001.915263","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915263","url":null,"abstract":"The ELITE (Essential Library In Technology Evolution) design methodology of foundation IP (Intellectual Property) for synthesis quality is presented in this paper. The design idea is derived from RISC (Reduced Instruction Set Computer) design philosophy in computer architecture. After analyzing the use rate of each cell with benchmarks, it shows that too many cells in a library not only increase the loading on library development and maintenance but also affect the quality of the logic synthesis. The ELITE design methodology proposes removing unused and rarely used cells from original library, then composing the most frequently used cells by logic synthesis tool to a new ELITE library. Due to fewer cells in a library, designers can significantly reduce the development time of cell library, shorten design time and pay more attention to improve the quality of the cell library with deep submicron process characteristics. Moreover, the experimental results show that, when ELITE libraries are used in logic synthesis the speed measurements improve 14.22% to 17.35% and the area measurements decrease 13.98% to 15.5% in unconstraint condition. The experiments of ELITE library with real industrial RTL designs also shown that the ELITE library has almost equal synthesis results when it is compared to conventional library with aggressive constraints. However, there are only 34 cells in ELITE library compared with 470 ones in the original library.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115662248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simulation using code-perturbation: black- and white-box approach 使用代码摄动的模拟:黑盒和白盒方法

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915204

Zan Yang, Byeong Min, G. Choi

引用次数: 1

Verification of embedded phase-locked loops 嵌入式锁相环的验证

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915245

T. Egan, S. Mourad

引用次数: 0

A system for automatic recording and prediction of design quality metrics 一个自动记录和预测设计质量指标的系统

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915210

A. Kahng, S. Mantik

引用次数: 21

Modeling of substrate noise injected by digital libraries 数字图书馆注入基板噪声的建模

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915276

S. Zanella, A. Neviani, E. Zanoni, Paolo Miliozzi, E. Charbon, C. Guardiani, L. Carloni, A. Sangiovanni-Vincentelli

{"title":"Modeling of substrate noise injected by digital libraries","authors":"S. Zanella, A. Neviani, E. Zanoni, Paolo Miliozzi, E. Charbon, C. Guardiani, L. Carloni, A. Sangiovanni-Vincentelli","doi":"10.1109/ISQED.2001.915276","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915276","url":null,"abstract":"Switching noise is one of the major sources of timing errors and functional hazards in logic circuits. It is caused by the cumulative effect of microscopic spurious currents arising in all devices during logic transitions. These currents are injected into the substrate and in supply lines, resulting in significant ripple noise. Individually, such micro-currents do not usually cause catastrophic failures. However, cumulatively, they can impact power supply and substrate potential across the chip. Thus, the electrical behavior of sensitive digital and analog circuits can be significantly changed, hence limiting circuit performance. The analysis of switching noise at a macroscopic level requires one to accurately compute models for all microscopic spurious currents, known as noise signatures. The challenge is to simultaneously account for a myriad of parameters and their process variations in a compact and accurate model. To address this problem, a new methodology based on response surface methodology and orthogonal polynomial approximation is proposed. Experimental results on a 0.35 /spl mu/m library show that the methodology is capable of accurately approximating noise signatures with a single analytical formula. A library of such formulae has been created and it is being used to accurately characterize switching noise at the macroscopic level.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126941198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Assessment of true worst case circuit performance under interconnect parameter variations 互连参数变化下真最坏情况下电路性能的评估

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915267

E. Acar, L. Pileggi, S. Nassif, Y. Liu

引用次数: 26

A fast coupling aware delay estimation scheme based on simplified circuit model 一种基于简化电路模型的快速耦合感知延迟估计方案

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915217

N. Lu, I. Hajj

引用次数: 0