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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献

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RC power bus maximum voltage drop in digital VLSI circuits 数字VLSI电路中RC电源总线的最大电压降
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.915238
G. Bai, S. Bobba, I. Hajj
{"title":"RC power bus maximum voltage drop in digital VLSI circuits","authors":"G. Bai, S. Bobba, I. Hajj","doi":"10.1109/ISQED.2001.915238","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915238","url":null,"abstract":"This paper presents an input-independent method for finding bounds on the voltage drop in RC power bus in digital VLSI circuits. The voltage at power bus nodes is expressed in term of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous HL and LH switching in a clock subinterval. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115119617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design, integration and validation of heterogeneous systems 异构系统的设计、集成和验证
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.915237
Steffen Klupsch
{"title":"Design, integration and validation of heterogeneous systems","authors":"Steffen Klupsch","doi":"10.1109/ISQED.2001.915237","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915237","url":null,"abstract":"The work presented in this paper aims at improving technical products which are known as heterogeneous systems. Today many products consist of electronic parts and interfaces to the real world which include sensors and non-electrical actuators. As the miniaturization continues the interrelation between the system elements is getting more important - and the system integration is getting more difficult. Therefore, integration issues must be considered during early phases of the system development. Furthermore, there is a strong need for design flows which support maintenance phases and regular product updates. The overall optimization goals are an increase of product quality and a reduction of development time.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127635499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy efficient signaling in deep submicron CMOS technology 深亚微米CMOS技术中的高能效信号
Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.915250
I. Dhaou, H. Tenhunen, V. Sundararajan, K. Parhi
{"title":"Energy efficient signaling in deep submicron CMOS technology","authors":"I. Dhaou, H. Tenhunen, V. Sundararajan, K. Parhi","doi":"10.1109/ISQED.2001.915250","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915250","url":null,"abstract":"In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeater insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeater insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25 /spl mu/m, 2.5 V, 6-metal-layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5 V down to 1.5 K.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131838091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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