Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献_第7页

HW-SW co-design and verification of a multi-standard video and image codec HW-SW协同设计和验证多标准视频和图像编解码器

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915261

R. Llopis, M. Oosterhuis, R. Sethuraman, P. Lippens, A. V. D. Werf, S. Maul, Jim Lin

引用次数: 13

Timing yield estimation from static timing analysis 基于静态时序分析的时序产率估计

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915268

A. Gattiker, S. Nassif, R. Dinakar, C. Long

引用次数: 122

Spice model quality: process development viewpoint 香料模型质量:过程发展观点

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915274

P. Bendix

引用次数: 1

CAD issues for CMOS VLSI design in SOI SOI中CMOS VLSI设计的CAD问题

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915213

K. Shepard

引用次数: 5

A hardware and software monitor for high-level system-on-chip verification 用于高级片上系统验证的硬件和软件监视器

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915206

Mohammed El Shobaki, L. Lindh

{"title":"A hardware and software monitor for high-level system-on-chip verification","authors":"Mohammed El Shobaki, L. Lindh","doi":"10.1109/ISQED.2001.915206","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915206","url":null,"abstract":"Verification of today's Systems-on-Chip (SoC) occurs at low abstraction-levels, typically at register-transfer level (RTL). As the complexity of SoC designs grows, it is increasingly important to move verification to higher abstraction-levels. Hardware/software co-simulation is a step in this direction, but is not sufficient due to inaccurate processor models, and slow hardware simulation speeds. System-level monitoring commonly used for event-based software debugging, provides information about task scheduling events, inter-task communication and synchronisation, semaphores/resources, I/O interrupts, etc. We present MAMon, a monitoring system that can both monitor the logic-level and the system-level in single/multiprocessor SoCs. A small hardware probe-unit is integrated in the SoC design and connects via a parallel-port link to a host-based monitoring tool environment. The probe-unit collects all events in the target system in run-time, and time-stamps them with a resolution of 1 /spl mu/s. The events are then stored in a database on the host for further processing. The paper will describe MAMon and how it works for software and hardware monitoring. The paper also describe how system-level monitoring can be achieved non-instrusively by using a hardware-based real-time kernel.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

HRM-a hierarchical simulator for full-chip power network reliability analysis 全芯片电网可靠性分析的分层仿真器

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915248

Yi-Min Jiang, Han Young Koh, K. Cheng

{"title":"HRM-a hierarchical simulator for full-chip power network reliability analysis","authors":"Yi-Min Jiang, Han Young Koh, K. Cheng","doi":"10.1109/ISQED.2001.915248","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915248","url":null,"abstract":"This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the transistor level, this method first simulates each top-level block in the design individually to derive macro-models of the blocks. For standard-cell blocks in the design, gate-level simulation is used to derive the switching profiles of all cells in the blocks. For full-custom blocks embedded in the design, transistor-level power network simulation is used. Based on the block-level simulation results, the simulated blocks are modeled as a set of current sources along with simplified but equivalent power network RCs. Top-level simulation is then performed based on the network consisting of the top-level power net RCs and the macro-models of the blocks. To macro-model the standard-cell blocks for power network analysis, this paper proposes a modeling technique to derive the power-network model which can accurately characterize the impact of the cell switching activity on the current and voltage of the entire power network. Experimental results on two industrial structured-custom-designs are presented. The results indicate that the proposed method, compared with an industrial power network simulator, significantly reduces the CPU runtime and memory requirement for power network simulation, maintaining small discrepancies.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Complex reliability evaluation of voters for fault tolerant designs 容错设计选择器的复杂可靠性评价

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915252

M. Radu, D. Pitica, Radu Munteanu, C. Posteuca

引用次数: 4

Scripting for EDA tools: a case study EDA工具的脚本编写:一个案例研究

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915211

Pinhong Chen, K. Keutzer, D. Kirkpatrick

{"title":"Scripting for EDA tools: a case study","authors":"Pinhong Chen, K. Keutzer, D. Kirkpatrick","doi":"10.1109/ISQED.2001.915211","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915211","url":null,"abstract":"Now to integrate EDA tools to enable interoperability and ease of use has been a very time-consuming and complicated job. Conventionally, each tool comes with a unique and simple set of commands for interactive use such as Sis, Vis, and Magic, but it lacks full programming capability of a scripting language. Also, it discourages further exploration to the underlying system functionality. Not only the code is hard to reuse, but also rapid prototyping of a new algorithm is impossible. A new algorithm may still take years to develop, which has to start from scratch and struggles between various formats. In this paper, we study and address how to easily integrate those application program interface (API)'s into most popular scripting languages such as Tcl or Perl. This enables a full scripting or programming language capability into a tool, and most important of all, any tool can be interoperated over a uniform platform on an API level. Rapid prototyping of a new algorithm thus becomes much easier and faster. It also promotes software reuse. Many existing extension packages for the scripting languages can be therefore integrated such as Tk for graphic user interface (GUI), and CPAN collection for various Perl applications. From a standpoint of high software quality this approach also provides a very good vehicle for comprehensive testing of each API in an EDA tool.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121369949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

High-quality FPGA designs through functional decomposition with sub-function input support selection based on information relationship measures 通过功能分解和基于信息关系度量的子功能输入支持选择来设计高质量的FPGA

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915264

A. Chojnacki, L. Józwiak

{"title":"High-quality FPGA designs through functional decomposition with sub-function input support selection based on information relationship measures","authors":"A. Chojnacki, L. Józwiak","doi":"10.1109/ISQED.2001.915264","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915264","url":null,"abstract":"Functional decomposition seems to be the most effective circuit synthesis approach for look-up table (LUT) FPGAs, (C)PLDs and complex gates. Since LUT FPGAs are used in numerous important applications and constitute a foundation for the novel re-configurable system-on-a-chip platforms, an adequate synthesis for this target is of primary importance for the modern system industry. In the functional decomposition targeting LUT FPGAs, the circuit is constructed by recursively decomposing a given function and its sub-functions until each of the resulting sub-functions can be directly implemented with a LUT. The impact support selection for the sub-functions that are constructed in this process decides the quality of the resulting multi-level circuit to a high degree. In this paper; we propose a new effective method for the sub-function input support selection and discuss its application in our circuit synthesis tool that targets LUT-based FPGAs. The experimental results demonstrate that the proposed approach lends to extremely fast and very small circuits. The circuits consume on average over 2 times less logic blocks (CLBs) and are over 1.5 times faster than the circuits produced by the best state-of-the-art commercial tools.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125642144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A global driver sizing tool for functional crosstalk noise avoidance 一个用于功能性串扰噪声避免的全局驱动尺寸工具

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.915221

M. Becer, D. Blaauw, S. Sirichotiyakul, C. Oh, V. Zolotov, Jingyan Zuo, R. Levy, I. Hajj

引用次数: 7