HRM-a hierarchical simulator for full-chip power network reliability analysis

Abstract

This paper presents a novel hierarchical simulation method for analyzing the power network reliability. Instead of performing full-chip simulation at the transistor level, this method first simulates each top-level block in the design individually to derive macro-models of the blocks. For standard-cell blocks in the design, gate-level simulation is used to derive the switching profiles of all cells in the blocks. For full-custom blocks embedded in the design, transistor-level power network simulation is used. Based on the block-level simulation results, the simulated blocks are modeled as a set of current sources along with simplified but equivalent power network RCs. Top-level simulation is then performed based on the network consisting of the top-level power net RCs and the macro-models of the blocks. To macro-model the standard-cell blocks for power network analysis, this paper proposes a modeling technique to derive the power-network model which can accurately characterize the impact of the cell switching activity on the current and voltage of the entire power network. Experimental results on two industrial structured-custom-designs are presented. The results indicate that the proposed method, compared with an industrial power network simulator, significantly reduces the CPU runtime and memory requirement for power network simulation, maintaining small discrepancies.