M. Becer, D. Blaauw, S. Sirichotiyakul, C. Oh, V. Zolotov, Jingyan Zuo, R. Levy, I. Hajj
{"title":"一个用于功能性串扰噪声避免的全局驱动尺寸工具","authors":"M. Becer, D. Blaauw, S. Sirichotiyakul, C. Oh, V. Zolotov, Jingyan Zuo, R. Levy, I. Hajj","doi":"10.1109/ISQED.2001.915221","DOIUrl":null,"url":null,"abstract":"As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures that can be caused by coupling noise. In this paper, we present a global driver sizing tool which can be used in a complete noise avoidance tool along with other techniques such as wire spacing and wire sizing. The proposed approach is used along with ClariNet, which is a recent noise analysis tool, in a greater effort towards a total signal integrity solution. We first present the analytical, linear interconnect model used. We then show how this model is used to provide necessary information for global driver sizing along with our novel algorithm. We finally present results on two industrial circuits including a large high performance control block.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A global driver sizing tool for functional crosstalk noise avoidance\",\"authors\":\"M. Becer, D. Blaauw, S. Sirichotiyakul, C. Oh, V. Zolotov, Jingyan Zuo, R. Levy, I. Hajj\",\"doi\":\"10.1109/ISQED.2001.915221\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures that can be caused by coupling noise. In this paper, we present a global driver sizing tool which can be used in a complete noise avoidance tool along with other techniques such as wire spacing and wire sizing. The proposed approach is used along with ClariNet, which is a recent noise analysis tool, in a greater effort towards a total signal integrity solution. We first present the analytical, linear interconnect model used. We then show how this model is used to provide necessary information for global driver sizing along with our novel algorithm. We finally present results on two industrial circuits including a large high performance control block.\",\"PeriodicalId\":110117,\"journal\":{\"name\":\"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2001.915221\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2001.915221","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A global driver sizing tool for functional crosstalk noise avoidance
As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures that can be caused by coupling noise. In this paper, we present a global driver sizing tool which can be used in a complete noise avoidance tool along with other techniques such as wire spacing and wire sizing. The proposed approach is used along with ClariNet, which is a recent noise analysis tool, in a greater effort towards a total signal integrity solution. We first present the analytical, linear interconnect model used. We then show how this model is used to provide necessary information for global driver sizing along with our novel algorithm. We finally present results on two industrial circuits including a large high performance control block.