Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献_第6页

Noise model for multiple segmented coupled RC interconnects 多分段耦合RC互连的噪声模型

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915219

A. Kahng, S. Muddu, Niranjan Pol, D. Vidhani

{"title":"Noise model for multiple segmented coupled RC interconnects","authors":"A. Kahng, S. Muddu, Niranjan Pol, D. Vidhani","doi":"10.1109/ISQED.2001.915219","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915219","url":null,"abstract":"The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. We present simple and improved analytical models for noise phenomena due to coupling capacitance. We extend the /spl Pi/ model presented previously to accommodate a segmented aggressor. We also include a linear driver resistance in the modeling of both victims and aggressors to measure their estimate on peak noise. Finally, we extend this model to multiple segmented aggressors by superposing noise contributions of individual aggressors and sweeping the result in the time domain to determine peak noise (in contrast to adding the individual peak noise values for individual aggressors). Accuracy in the results depends greatly on actual positioning of victim-aggressor overlaps. We find that previous models that assume aggressors run parallel to the victim net for its entire length do not yield peak noise results nearly as close to SPICE-computed values. We also find that inclusion of driver resistance in the model improves accuracy. Our noise model for a single segmented aggressor is within /spl sim/16% of SPICE. Results for two segmented aggressors are within acceptable tolerances with respect to SPICE, but error increases with the number of aggressors. We note that these results are almost always pessimistic.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125119843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A compact layout technique for reducing switching current effects in high speed circuits 一种在高速电路中减少开关电流效应的紧凑布局技术

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915231

J. Montiel-Nelson, V. Armas, R. Sarmiento, A. Núñez

引用次数: 2

Power trends and performance characterization of 3-dimensional integration for future technology generations 面向未来技术世代的三维集成电源趋势和性能表征

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915230

R. Zhang, K. Roy, Cheng-Kok Koh, D. Janes

{"title":"Power trends and performance characterization of 3-dimensional integration for future technology generations","authors":"R. Zhang, K. Roy, Cheng-Kok Koh, D. Janes","doi":"10.1109/ISQED.2001.915230","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915230","url":null,"abstract":"3-D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into 3-D circuit architecture and performance. One of the purposes of realizing 3-D integration is to reduce the interconnect complexity and delay of 2-D, which are widely avowed as the barriers to the continued performance gain in the future technology generations. Therefore, in this paper, we present a stochastic 3-D interconnect model, study the impact of 3-D integration on circuit performance and power consumption. We show that 3-D structures effectively reduce the number of long delay nets, significantly reduce the number of repeaters, and dramatically improve the circuit performance. With 3-D integration, circuits can be clocked at frequencies much higher (double, even triple) than with 2-D. However, we also show that the impacts of vertical wires on chip area and interconnect delay can be limiting factors on the vertical integration of device layers; and that 3-D integration offers limited relief of power consumption.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121037973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Chip-level substrate noise analysis with network reduction by fundamental matrix computation 基于基本矩阵计算的网络降维芯片级衬底噪声分析

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915275

Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, A. Iwata

引用次数: 15

A fully qualified analog design flow for nonvolatile memories technologies 一个完全合格的模拟设计流程的非易失性存储器技术

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915270

P. Daglio, M. Araldi, M. Morbarigazzi, C. Roma

引用次数: 0

Applying Moore's technology adoption life cycle model to quality of EDA software 将Moore的技术采用生命周期模型应用于EDA软件质量

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915209

G. Ben-Yaacov, Edward P. Stone, R. Goldman

引用次数: 3

Automatic functional vector generation using the interacting FSM model 使用交互FSM模型自动生成功能向量

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915258

C. Liu, Chia-Chih Yen, Jing-Yang Jou

引用次数: 3

Test pattern generators for distributed and embedded built-in self-test at register transfer level 测试模式生成器的分布式和嵌入式内置自检在寄存器传输水平

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915236

Vlado Vorisek

引用次数: 0

Revisiting the classical fault models through a detailed analysis of realistic defects 通过对实际缺陷的详细分析，重新审视经典故障模型

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915256

M. Renovell

引用次数: 2

Concrete impact of formal verification on quality in IP design and implementation 形式验证对IP设计和实施质量的具体影响

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915203

U. Rossi, A. Fedeli, M. Boschini, F. Toto

引用次数: 0