Concrete impact of formal verification on quality in IP design and implementation

The application of formal methods to the logic verification of electronic circuits is meant for increasing the coverage obtained by the traditional verification techniques. This concept is quite popular in the design community but requires some guidelines in order to be implemented. The purpose of this work is to show that the advantage of equivalence checking and model checking, by far the two more important techniques in logic formal verification, resides in the capability of powerful and concise modeling of the environment driving the verification process and in the capability of concise description of the expected behavior; such characteristics often achieve exhaustiveness which is difficult to reach with other verification techniques. A unified vision of environment modeling in the combinational and sequential worlds is proposed; results of application of the underlying ideas are reported on real industrial cases.