Noise model for multiple segmented coupled RC interconnects

A. Kahng, S. Muddu, Niranjan Pol, D. Vidhani
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引用次数: 20

Abstract

The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. We present simple and improved analytical models for noise phenomena due to coupling capacitance. We extend the /spl Pi/ model presented previously to accommodate a segmented aggressor. We also include a linear driver resistance in the modeling of both victims and aggressors to measure their estimate on peak noise. Finally, we extend this model to multiple segmented aggressors by superposing noise contributions of individual aggressors and sweeping the result in the time domain to determine peak noise (in contrast to adding the individual peak noise values for individual aggressors). Accuracy in the results depends greatly on actual positioning of victim-aggressor overlaps. We find that previous models that assume aggressors run parallel to the victim net for its entire length do not yield peak noise results nearly as close to SPICE-computed values. We also find that inclusion of driver resistance in the model improves accuracy. Our noise model for a single segmented aggressor is within /spl sim/16% of SPICE. Results for two segmented aggressors are within acceptable tolerances with respect to SPICE, but error increases with the number of aggressors. We note that these results are almost always pessimistic.
多分段耦合RC互连的噪声模型
高速VLSI电路的性能越来越受到互连耦合噪声的限制。我们提出了由耦合电容引起的噪声现象的简单和改进的分析模型。我们扩展了之前提出的/spl Pi/模型,以适应分段攻击器。我们还在受害者和攻击者的建模中包括线性驱动电阻,以测量他们对峰值噪声的估计。最后,我们通过叠加单个干扰源的噪声贡献并在时域中扫描结果以确定峰值噪声(与添加单个干扰源的单个峰值噪声值相反),将该模型扩展到多个分段干扰源。结果的准确性在很大程度上取决于受害者-攻击者重叠的实际位置。我们发现以前的模型假设攻击者在整个长度上与受害者网平行运行,并不能产生接近spice计算值的峰值噪声结果。我们还发现,在模型中加入驱动电阻可以提高精度。我们对单个分段攻击者的噪声模型在SPICE的/ sp1sim /16%以内。两个分段攻击者的结果在SPICE的可接受范围内,但误差随着攻击者的数量而增加。我们注意到,这些结果几乎总是悲观的。
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