测试模式生成器的分布式和嵌入式内置自检在寄存器传输水平

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI:10.1109/ISQED.2001.915236

Vlado Vorisek

{"title":"测试模式生成器的分布式和嵌入式内置自检在寄存器传输水平","authors":"Vlado Vorisek","doi":"10.1109/ISQED.2001.915236","DOIUrl":null,"url":null,"abstract":"The poster presents Ph.D. thesis in the area of test pattern generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders, subtracters, multiplexers, comparators at register transfer level (RTL) of circuit description.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Test pattern generators for distributed and embedded built-in self-test at register transfer level\",\"authors\":\"Vlado Vorisek\",\"doi\":\"10.1109/ISQED.2001.915236\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The poster presents Ph.D. thesis in the area of test pattern generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders, subtracters, multiplexers, comparators at register transfer level (RTL) of circuit description.\",\"PeriodicalId\":110117,\"journal\":{\"name\":\"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design\",\"volume\":\"99 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2001.915236\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2001.915236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

这是一篇关于测试模式生成器(TPGs)在分布式和嵌入式内置自检(BIST)中的应用的博士论文。本研究的目的是为电路描述的寄存器传输电平(RTL)的加法器、减法器、多路复用器、比较器等基本算术元件设计一种通用方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Test pattern generators for distributed and embedded built-in self-test at register transfer level

The poster presents Ph.D. thesis in the area of test pattern generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders, subtracters, multiplexers, comparators at register transfer level (RTL) of circuit description.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

自引率

0.00%

发文量