基于基本矩阵计算的网络降维芯片级衬底噪声分析

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI:10.1109/ISQED.2001.915275

Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, A. Iwata

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引用次数: 15

摘要

基于基本矩阵(f矩阵)的衬底网格缩减技术被纳入芯片级衬底噪声仿真方法。0.6 /spl mu/m CMOS衬底噪声评估芯片的系统级等效电路模型与100 ps 100 /spl mu/V衬底噪声波形测量结果比较，仿真误差小于15%。

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Chip-level substrate noise analysis with network reduction by fundamental matrix computation

The fundamental matrix (F-matrix) based substrate mesh reduction technique is incorporated in a chip-level substrate noise simulation methodology. A system-level equivalent circuit model of a 0.6 /spl mu/m CMOS substrate noise evaluation chip demonstrates simulation errors of less than 15% by comparing it with 100 ps 100 /spl mu/V substrate noise waveform measurements.

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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

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