Chip-level substrate noise analysis with network reduction by fundamental matrix computation

Abstract

The fundamental matrix (F-matrix) based substrate mesh reduction technique is incorporated in a chip-level substrate noise simulation methodology. A system-level equivalent circuit model of a 0.6 /spl mu/m CMOS substrate noise evaluation chip demonstrates simulation errors of less than 15% by comparing it with 100 ps 100 /spl mu/V substrate noise waveform measurements.