Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design最新文献_第3页

Performance improvement for high speed devices using E-tests and the SPICE model 使用e -test和SPICE模型对高速器件进行性能改进

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915269

T. Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, J. Kong

引用次数: 2

Design on ESD protection circuit with very low and constant input capacitance 极低恒输入电容ESD保护电路的设计

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915233

Tung-Yang Chen, M. Ker

引用次数: 7

Using the boundary scan delay chain for cross-chip delay measurement and characterization of delay modeling flow 利用边界扫描延迟链进行跨片延迟测量和表征的延迟建模流程

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915253

J. Schmid, Timo Schüring, Christoph Smalla

{"title":"Using the boundary scan delay chain for cross-chip delay measurement and characterization of delay modeling flow","authors":"J. Schmid, Timo Schüring, Christoph Smalla","doi":"10.1109/ISQED.2001.915253","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915253","url":null,"abstract":"For ASICs/SOCs/lCs it is often very important to have an easily accessible delay measurements path for several reasons. The delay of a long path running across the whole chip through lots of instances (inverters, MUXes) makes it possible to measure the final process parameters of an ASIC/IC within the best and worst case production process window. This information is very important for production testing and assembly at the vendor site. But very often this information is also necessary at circuit pack level, system test level and even in the field - when in the case of problems (functionality, timing, debugging) it should be known which \"quality level\" the ASIC/IC device has reached. Also for characterization of the delay modeling during the different design phases (estimation, floorplanning, trial and final layout) such a dedicated delay path may help in qualifying the delay models. We propose to use a new standard methodology to address these issues by definition of a dedicated delay path. It is called \"Boundary Scan Delay Chain\" (BSDC). We use the Boundary Scan data register according to IEEE1149.1 to get a delay chain across the chip. Only a slight modification of the boundary scan cell (e.g. BC 1, BC 4) is necessary. The resulting new functionality still conforms to IEEE1149.1.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125577912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Soft core based model of a microcomputer family 基于软核的微机系列模型

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915232

N. Q. Trung, K. Siekierska

引用次数: 1

RC power bus maximum voltage drop in digital VLSI circuits 数字VLSI电路中RC电源总线的最大电压降

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915228

G. Bai, S. Bobba, I. Hajj

引用次数: 10

Diversity techniques for concurrent error detection 并发错误检测的分集技术

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915234

S. Mitra, E. McCluskey

引用次数: 23

Acceleration of DAB chipset development by deployment of a real-time rapid prototyping approach based on behavioral synthesis 通过部署基于行为综合的实时快速原型方法加速DAB芯片组的开发

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915262

M. Speitel, M. Schlicht, Martin Leyh

{"title":"Acceleration of DAB chipset development by deployment of a real-time rapid prototyping approach based on behavioral synthesis","authors":"M. Speitel, M. Schlicht, Martin Leyh","doi":"10.1109/ISQED.2001.915262","DOIUrl":"https://doi.org/10.1109/ISQED.2001.915262","url":null,"abstract":"The development of a new digital communication system has the twofold goal to achieve all traditional requirements from the end user prospective and to offer a huge potential of additional services compared with existing analog systems. The extremely demanding time frame for the introduction of such a system requires a development approach reducing the design risk to a minimum especially for the end user receivers. As an integral part of the terminal the digital baseband processor is one of the most challenging receiver components in terms of development and validation effort. The complexity of the ASIC design with initially estimated 500,000 to 1,000,000 gate equivalents has driven the deployment of a real-time prototyping system. To assure real-time and identical functionality on both FPGA prototype and ASIC behavioral synthesis was used for timing-critical and computationally intensive building blocks. The design and validation methodology was successfully implemented. The ASIC will be introduced in the first generation of mobile radio receivers for digital audio broadcasting in the United States.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131634319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A model for crosstalk noise evaluation in deep submicron processes 深亚微米工艺串扰噪声评价模型

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915218

P. Bazargan-Sabet, F. Ilponse

引用次数: 13

Models for interconnect capacitance extraction 互连电容提取模型

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915222

A. Husain

引用次数: 28

VSIA quality metrics for IP and SoC IP和SoC的VSIA质量指标

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI: 10.1109/ISQED.2001.915243

M. Birnbaum, Charlene C. Johnson

引用次数: 14