RC power bus maximum voltage drop in digital VLSI circuits

This paper presents an input-independent method for finding bounds on the voltage drop in RC power bus in combinational macro-block circuits. The voltage at power bus nodes is expressed in terms of gate currents using sensitivity analysis. Circuit timing information, functionality and logic dependencies are employed to find maximum simultaneous high-to-low, and low-to-high switching in a subinterval of a clock cycle. The sensitivity information together with an optimization procedure are applied to find bounds on the voltage drop in targeted bus nodes. The effects of signal statistical variations on the results are automatically included in our method. Comparisons to exhaustive HSPICE simulation of circuits extracted from layout are used to validate our approach.