Models for interconnect capacitance extraction

Abstract

Commonly used numerical methods in capacitance extraction both for small and large circuit blocks are reviewed for a VLSI design. Boundary element based field solvers can effectively be used for small structures but can not be used for large structures because of large grid requirement. Field solvers based on random walk method are more appropriate for large structures but still they are quite slow in comparison to analytic capacitance models, which are generally applied for chip level extractions. Accounting for 3D fringing fields has become essential in analytic models for accurate extraction of current VLSI technologies.