Trading bitwidth for array size: a unified reconfigurable arithmetic processor design

This paper presents a novel unified run-time reconfigurable arithmetic processor design scheme. It provides novel computational trade-offs between array/matrix size and input data item bitwidth, and efficiently performs multiple types of arithmetic operations in pipeline within a single hardware-reusable processor. The proposed computations include inner product evaluation, matrix multiplication, and evaluation of polynomial. More specifically, we show that the minimum hardware platform can be easily reconfigured to complete: [1] the inner products of two input arrays with several combinations of array dimension and precision, including input arrays of 256 4-bit items, 64 8-bit items, 16 16-bit items, 4 32-bit items and I 64-bit item; (2) the product of matrices X/sub nk/ and Y/sub km/ for any integers n, k, m and any item precision b ranging from 4 to 64 bits, including input arrays of X/sub 16/spl times/16/ Y/sub 16/spl times/16/ of 4-bit items, X/sub 8/spl times/8/ and Y/sub 8/spl times/8/ of 8-bit items, X/sub 4/spl times/4/, Y/sub 4/spl times/4/ of 16-bit items, X/sub 2/spl times/2/ and Y/sub 2/spl times/2/ of 32-bit items and the product of two 64-bit numbers; (3) the polynomial evaluations at any given point x, with several combinations of the polynomial degree N and evaluation point number precision p, including polynomial degree and item precision options of N=64, p=13, N=16, p=16, and N=4, p=32.