An effective current source cell model for VDSM delay calculation

Abstract

We present a new approach to model delay of the digital cell in very deep submicron (VDSM) IC designs. It provides higher accuracy for both delay and transition time than the conventional effective capacitance approximation. The cell is modeled by an effective current source that emulate the behavior of the transistor network. The proposed model is based upon the standard timing tables of the characterized cell.