带有外设I/O的asic的I/O单元放置和电气检查方法

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI:10.1109/ISQED.2001.915208

Gulsun Yasar, Charles Chiu, R. Proctor, J. Libous

{"title":"带有外设I/O的asic的I/O单元放置和电气检查方法","authors":"Gulsun Yasar, Charles Chiu, R. Proctor, J. Libous","doi":"10.1109/ISQED.2001.915208","DOIUrl":null,"url":null,"abstract":"Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.","PeriodicalId":110117,"journal":{"name":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os\",\"authors\":\"Gulsun Yasar, Charles Chiu, R. Proctor, J. Libous\",\"doi\":\"10.1109/ISQED.2001.915208\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.\",\"PeriodicalId\":110117,\"journal\":{\"name\":\"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-03-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2001.915208\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2001.915208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

优化的I/O电池放置技术考虑了配电网络中的电迁移(EM)、IR下降和dI/dt噪声问题。本文描述了在设计过程早期使用的快速简便的电子检查算法，以验证I/O放置是否符合放置指南，并解释了检查工具使用的I/O单元放置相关角色的详细信息。使用这些技术和方法可以保证高质量的asic。

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I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os

Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.

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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

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