“为验证而设计”的方法

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design Pub Date : 2001-03-26 DOI:10.1109/ISQED.2001.915205

F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi

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引用次数: 11

摘要

市场上出现了新的工具，可以帮助缓解问题并提高当今复杂系统的功能验证的质量。描述了利用这些工具的方法，并将其与特定项目中遵循的传统方法进行了比较。范围限于功能验证，但从块级跨越到系统级。

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A "design for verification" methodology

New tools are becoming available on the market that help alleviate the problem and improve the quality of functional verification of today's complex systems. A methodology that makes use of such tools is described and compared to the traditional approach followed in the context of a specific project. The scope is limited to functional verification but spans from block- to system level.

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Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

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