I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os

Abstract

Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.