Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process

Abstract

An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS ICs is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-/spl mu/m shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS ICs, but still to maintain high enough latchup immunity in bulk CMOS ICs.