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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献

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Automated synthesis of a multiple-sequence test generator using 2-D LFSR 用二维LFSR自动合成多序列测试发生器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722807
Xin Yuan, C.-i.H. Chen
{"title":"Automated synthesis of a multiple-sequence test generator using 2-D LFSR","authors":"Xin Yuan, C.-i.H. Chen","doi":"10.1109/ASIC.1998.722807","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722807","url":null,"abstract":"Given a set of pre-computed test vectors obtained by an automatic test pattern generation (ATPG) tool for detecting random-pattern-resistant faults or particular hard-to-test faults presented in a circuit under test (CUT), a simple test generator based on a 2D linear feedback shift register (LFSR) structure is presented in this paper to generate a given test, followed by random patterns. Not only generating deterministic test vectors, the synthesized test generator also has a 2-D LFSR structure which generates better random patterns than a conventional LFSR. Experimental results are provided for practical circuits to demonstrate the effectiveness of the scheme. The scheme allows a trade-off between test vector storage and test hardware. A synthesis procedure of designing this test generator is presented.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123803082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Digital design of discrete wavelet transform for MPEG-4 MPEG-4离散小波变换的数字化设计
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723028
Z. Zhou, D. Hung
{"title":"Digital design of discrete wavelet transform for MPEG-4","authors":"Z. Zhou, D. Hung","doi":"10.1109/ASIC.1998.723028","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723028","url":null,"abstract":"It has been proposed to use the Discrete Wavelet Transform (DWT) in the draft MPEG-4 standard, which is expected play an important role in low bit-rate applications such as video telephony. A digital design for the DWT is presented in this paper. Related issues including the basic concept, boundary treatment, and the distributed arithmetic algorithm are addressed.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123815106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Methodology for process portable hard IP block creation using cell based array architecture 使用基于单元的阵列体系结构的过程便携式硬IP块创建方法
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722992
R. Gopisetty, K. Hsu, A. Chakankar
{"title":"Methodology for process portable hard IP block creation using cell based array architecture","authors":"R. Gopisetty, K. Hsu, A. Chakankar","doi":"10.1109/ASIC.1998.722992","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722992","url":null,"abstract":"A methodology for hard IP creation and an automated \"process tuned\" migration of this IP block is presented. The flow for hard IP creation using the CBA Block Export Flow is presented. Salient features of this include automated IP block timing model creation and physical view creation allowing easy encapsulation of the IP core into a chip level environment. Following this, a flow for automatically porting this IP core so that it is optimally implemented in the target process using CBA Block Transport is presented.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115076766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The challenge of high-performance, deep-submicron design in a turnkey ASIC environment 在交钥匙专用集成电路环境中实现高性能、深亚微米设计的挑战
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722892
K. Shepard
{"title":"The challenge of high-performance, deep-submicron design in a turnkey ASIC environment","authors":"K. Shepard","doi":"10.1109/ASIC.1998.722892","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722892","url":null,"abstract":"In this paper, we review the trends and techniques that are shaping high-performance ASIC design in deep-submicron technology. The importance of interconnect in determining performance is breaking the clean division between logical and physical design, while noise analysis is becoming as important as timing analysis in ensuring correct functionality. The growing complexity of rules in precharacterized libraries is making analysis tools that understand transistors more attractive. In addition, new layout techniques allow libraries to be created dynamically, creating the opportunity for truly transistor-level synthesis. Domino logic and pass-transistor circuits promise to find their way into synthesis with increasing performance demands at the high end.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132960249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A single chip video coding system with embedded DRAM frame memory for stand-alone applications 一种用于独立应用的带有嵌入式DRAM帧存储器的单芯片视频编码系统
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723023
K. Herrmann, J. Hilgenstock, P. Pirsch
{"title":"A single chip video coding system with embedded DRAM frame memory for stand-alone applications","authors":"K. Herrmann, J. Hilgenstock, P. Pirsch","doi":"10.1109/ASIC.1998.723023","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723023","url":null,"abstract":"A video coding subsystem for monolithic integration in a 0.25 /spl mu/m CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 /spl mu/m CMOS technology. A system realization in 0.25 /spl mu/m CMOS technology is planned. Investigations show that a die size of less than 89 mm/sup 2/ for a single chip implementation can be achieved.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134496193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Self-tested self-synchronization by a two-phase input port 自检自同步由一个两相输入端口
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722987
F. Mu, C. Svensson
{"title":"Self-tested self-synchronization by a two-phase input port","authors":"F. Mu, C. Svensson","doi":"10.1109/ASIC.1998.722987","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722987","url":null,"abstract":"In high speed large systems, global clocking is used to protect clocked I/O from data read failure due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method implemented by a two-phase input port for parallel data transfer between blocks. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughput; less power consumption in clock distribution; no constraints on clock skew and system scale; easy in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, robust parallel data transfer between blocks with arbitrary local clock phases is achieved and the problem of global synchronization is avoided in designing high performance ULSI.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132378634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
System level interconnect power modeling 系统级互连电源建模
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723009
Yan Zhang, R. Y. Chen, W. Ye, M. J. Irwin
{"title":"System level interconnect power modeling","authors":"Yan Zhang, R. Y. Chen, W. Ye, M. J. Irwin","doi":"10.1109/ASIC.1998.723009","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723009","url":null,"abstract":"While power consumption of interconnects has become an important issue as technology scales, very few papers on power modeling of interconnects are available in the literature. This paper presents an architectural level interconnect power modeling method and applies it to a commercial chip that integrates a 16-bit DSP and a 32-bit RISC microcontroller. This power modeling method is applicable to any architecture if an architectural level description is provided. An architectural level simulator based on the commercial chip has been enhanced to generate the activity parameters for several signal processing benchmarks and some simple synthetic benchmarks at different technology feature sizes. The power measurements for all six global buses of the chip are reported.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Self-timed refreshing approach for dynamic memories 动态记忆的自定时刷新方法
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722887
J. Nyathi, J. Delgado-Frías
{"title":"Self-timed refreshing approach for dynamic memories","authors":"J. Nyathi, J. Delgado-Frías","doi":"10.1109/ASIC.1998.722887","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722887","url":null,"abstract":"Refreshing dynamic circuits must be carried out before stored voltages reach unacceptable levels. In this paper we present CMOS circuitry that can be used to sense the integrity of stored data, provide timely refreshing to these dynamic circuits and provide high performance. Differential amplifiers are used to provide the difference between a degrading stored voltage and a reference voltage. This difference gets converted to a single-ended output which serves as the refresh trigger. Memory arrays are used as test beds to verify the functionality and effectiveness of these circuits. The circuits considered in this paper are suitable for use in high speed, low power and high density memory arrays.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"4 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123807310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A sixth-order CMOS sigma-delta modulator 六阶CMOS sigma-delta调制器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722804
H. Y. San, S. M. Rezaul Hasan
{"title":"A sixth-order CMOS sigma-delta modulator","authors":"H. Y. San, S. M. Rezaul Hasan","doi":"10.1109/ASIC.1998.722804","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722804","url":null,"abstract":"A sixth-order sigma-delta modulator is presented. Sixth-order noise shaping is achieved though four stage cascaded noise cancellation network. Behavioral simulation shows that cascaded 2-1-1-2, (second order-first order-first order-second order) is very robust and suitable for VLSI implementation. An experimental prototype was fabricated using 2 /spl mu/m CMOS process by MOSIS. Measurement result shows that the modulator achieved 89 dB (14.8 bit) peak SNR and 92 dB (15.3 bit) dynamic range for 32 kHz bandwidth at a sampling rate of 1.024 MHz which corresponds to an oversampling ratio of 16. The modulator dissipates 79 mW at +/- 3.3 V supply voltage.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125326985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 440 MHz 16 bit counter in CMOS standard cells CMOS标准单元中的440 MHz 16位计数器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722966
B. Hoppe, C. Kroh, H. Meuth, M. Stohr
{"title":"A 440 MHz 16 bit counter in CMOS standard cells","authors":"B. Hoppe, C. Kroh, H. Meuth, M. Stohr","doi":"10.1109/ASIC.1998.722966","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722966","url":null,"abstract":"We present a high speed counter architecture, which operates in 0.7 /spl mu/m CMOS standard cells at a measured clock rate of 440 MHz. The basic architecture provides the following key features: (a) the speed performance is essentially limited only by the delay of a single flip-flop; (b) the counter state stabilizes to the actual state within a single clock cycle.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130439019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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