A 440 MHz 16 bit counter in CMOS standard cells

Abstract

We present a high speed counter architecture, which operates in 0.7 /spl mu/m CMOS standard cells at a measured clock rate of 440 MHz. The basic architecture provides the following key features: (a) the speed performance is essentially limited only by the delay of a single flip-flop; (b) the counter state stabilizes to the actual state within a single clock cycle.