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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献

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Analog And Mixed-signal 模拟和混合信号
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722796
M. Gaboury, P. R. Mukund
{"title":"Analog And Mixed-signal","authors":"M. Gaboury, P. R. Mukund","doi":"10.1109/ASIC.1998.722796","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722796","url":null,"abstract":"","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122020921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of standard cells used in low-power ASIC's exploiting the multiple-supply-voltage scheme 采用多电源电压方案的低功耗ASIC标准单元的设计
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722815
Jinn-Shyan Wang, Shang-Jyh Shieh, J. Wang, C. Yeh
{"title":"Design of standard cells used in low-power ASIC's exploiting the multiple-supply-voltage scheme","authors":"Jinn-Shyan Wang, Shang-Jyh Shieh, J. Wang, C. Yeh","doi":"10.1109/ASIC.1998.722815","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722815","url":null,"abstract":"ASIC design utilizing the multiple-supply-voltage (MSV) scheme has been shown to be efficient in reducing the power consumption. A new layout style of standard cells to be used in ASIC designs is proposed to effectively exploit the advantages afforded by the MSV scheme. Each standard cell is designed to use two power rails that are fed with different supply voltages. Then, the cells can be butted together arbitrarily no matter whether the cells are supplied from a high or low voltage, and the existing P&R tool can place and route the circuit as usual. As compared to the design with only one supply voltage, the average saving of power consumption of the new design (using the new cells and adopting the MSV scheme) is over 30%, but the average area overhead is only about 8%. Meanwhile, the average interconnection length is only increased by about 7.5%.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129709571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process ASIC制程的10b20mps 28mw CMOS ADC
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722803
A. Wada, K. Tani, Y. Matsushita, Y. Harada
{"title":"A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process","authors":"A. Wada, K. Tani, Y. Matsushita, Y. Harada","doi":"10.1109/ASIC.1998.722803","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722803","url":null,"abstract":"We have developed a 20 Msample/s 10 b CMOS ADC with a 2.4 V power supply, in 0.35 /spl mu/m 1-poly 2-Metal ASIC process without a special analog process, which is suitable for embedding in ASICs because of the small area (4.84 mm/sup 2/) and small power consumption. To realize this ADC we have developed a 2-step interstage amplifying pipeline system and new circuit technologies for residue amplifiers. The prototype chip was fabricated and was measured. It shows good linearity of less than /spl plusmn/1 LSB and 28 mW power consumption with 2.4 V at 20 MHz sampling.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115493318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic circuit synthesis using the Owens tool set 动态电路合成使用欧文斯工具集
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722903
M. J. Irwin, R.Y. Chen
{"title":"Dynamic circuit synthesis using the Owens tool set","authors":"M. J. Irwin, R.Y. Chen","doi":"10.1109/ASIC.1998.722903","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722903","url":null,"abstract":"This paper overviews the Owens CAD tool set developed at Penn State University and illustrates its ability to synthesize dynamic CMOS circuits. The CAD system includes: a cell compiler with transistor sizing and I/O direction annotation; a simulation tool based on the switch-level logic model; tools for multi-level logic optimization; and tools for format conversion which establish a connection with the netlist specification, truth tables, Boolean equations and VHDL. The Owens tool set is able to implement various CMOS structures such as static gates, dynamic gates and transmission gates. In particular, since it supports transistor sizing, it creates an efficient design environment for dynamic circuit implementation and optimization. To show this feature, this paper illustrates the application of the Owens tool set to the design of zipper CMOS adders and Manchester carry chain adders which are typical dynamic circuits.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124354672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Designing a Java microprocessor core using FPGA technology 利用FPGA技术设计一个Java微处理器内核
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722787
A. Kim, M. Chang
{"title":"Designing a Java microprocessor core using FPGA technology","authors":"A. Kim, M. Chang","doi":"10.1109/ASIC.1998.722787","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722787","url":null,"abstract":"Ever since its introduction from Sun Microsystems three years ago, Java has been widely accepted in the computing and Internet industry. However the run-time performance is still not good enough for Java to become a general purpose programming language. This paper shows how to implement a Java microprocessor core in silicon to speed up the execution of Java. For a reconfigurable and flexible design, the Field Programmable Gate Array (FPGA) is chosen as a target technology for the Java microprocessor. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA. The DFT technique is added for better testability.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124524131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The improvement of conditional sum adder for low power applications 低功耗条件加法器的改进
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722817
Kuo-Hsing Cheng, Shu-Min Chiang, Shun-Wen Cheng
{"title":"The improvement of conditional sum adder for low power applications","authors":"Kuo-Hsing Cheng, Shu-Min Chiang, Shun-Wen Cheng","doi":"10.1109/ASIC.1998.722817","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722817","url":null,"abstract":"The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122084286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
CMOS-based sensors and actuators 基于cmos的传感器和执行器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723047
F. Van Steenkiste, D. Maes, L. Haspeslagh, S. Sedky, P. Van Gerwen, S. Vandergroen, K. Baert
{"title":"CMOS-based sensors and actuators","authors":"F. Van Steenkiste, D. Maes, L. Haspeslagh, S. Sedky, P. Van Gerwen, S. Vandergroen, K. Baert","doi":"10.1109/ASIC.1998.723047","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723047","url":null,"abstract":"In many applications, up to millions of sensors or actuators have to be connected to the outside world, making the monolithic integration of circuits mandatory. Monolithic integration is also pursued for mass-produced transducers. Today, monolithic devices include visible and IR imagers, displays, inkjet heads, biochemical and physical sensors. Monolithic integration of transducer-specific processes (such as micromachining) with standard CMOS processes is possible, albeit at an increase of process complexity.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128355521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A voltage-regulated static keeper technique for high-performance ASICs 一种用于高性能asic的稳压静态保持技术
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723036
H. Kanno, T. Saeki, H. Abiko, A. Kubo, K. Tokashiki
{"title":"A voltage-regulated static keeper technique for high-performance ASICs","authors":"H. Kanno, T. Saeki, H. Abiko, A. Kubo, K. Tokashiki","doi":"10.1109/ASIC.1998.723036","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723036","url":null,"abstract":"A Voltage-Regulated Static Keeper (VRSK) technique is proposed. The VRSK can be applied to any dynamic circuit without size optimization and dissipates only one-third power of a static keeper. A 4-bit demultiplexer incorporating the VRSK can operate up to 2.0 GHz with a power consumption of only 5.8 mW.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Circuit techniques for high-speed and low-power multi-port SRAMs 高速低功耗多端口sram的电路技术
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722823
M. Khellah, M. Elmasry
{"title":"Circuit techniques for high-speed and low-power multi-port SRAMs","authors":"M. Khellah, M. Elmasry","doi":"10.1109/ASIC.1998.722823","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722823","url":null,"abstract":"This paper presents a new approach based on current-mode to reduce the energy and improve the speed of write and read accesses in multi-port SRAMs. The design of a pipelined 32/spl times/64 register file that utilizes the above technique is described. Simulation results in a 0.6 /spl mu/m CMOS technology show that the register file can operate at a 500 MHz frequency using a 2.3 V supply.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128536281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Reusable Architectures And Intellectual Property 可重用架构和知识产权
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722989
R. Krishnamurthy, Shih-Lien Lu
{"title":"Reusable Architectures And Intellectual Property","authors":"R. Krishnamurthy, Shih-Lien Lu","doi":"10.1109/ASIC.1998.722989","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722989","url":null,"abstract":"The papers in this section describe reusable architectures and address some of the important issues of intellectual property. The first paper presents soft cores for well-established industrystandard microcontrollers. The authors discuss the development effort, their verification strategy and the simulation environment as well as the IP difficulties encountered. The second paper focuses on a methodology for producing process portable hard cores using a cell based array architecture. The Cell Based Array Block Expert flow is presented that can be wed to automatically port IP cores so that they are optimally implemented in a target process.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128718322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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