A voltage-regulated static keeper technique for high-performance ASICs

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI:10.1109/ASIC.1998.723036

H. Kanno, T. Saeki, H. Abiko, A. Kubo, K. Tokashiki

引用次数: 7

Abstract

A Voltage-Regulated Static Keeper (VRSK) technique is proposed. The VRSK can be applied to any dynamic circuit without size optimization and dissipates only one-third power of a static keeper. A 4-bit demultiplexer incorporating the VRSK can operate up to 2.0 GHz with a power consumption of only 5.8 mW.

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一种用于高性能asic的稳压静态保持技术

提出了一种稳压静态保持器(VRSK)技术。VRSK可以应用于任何不需要优化尺寸的动态电路，功耗仅为静态keeper的三分之一。采用VRSK的4位解复用器可以在2.0 GHz的频率下工作，功耗仅为5.8 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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