低功耗条件加法器的改进

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI:10.1109/ASIC.1998.722817

Kuo-Hsing Cheng, Shu-Min Chiang, Shun-Wen Cheng

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引用次数: 12

摘要

作者描述了一种新的低功耗应用条件和规则。这种条件加法器对实现高速算术系统特别有吸引力。新的条件和加法规则可以减少加法器设计中的内部节点和多路器数量。使用不同的电源电压和电路结构来实现新的条件加法器。结果表明，可节省约10% ~ 25%的功率延迟产品。

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The improvement of conditional sum adder for low power applications

The authors describe a new conditional-sum rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It is shown that about 10% to 25% power-delay product is saved.

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来源期刊

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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