Self-tested self-synchronization by a two-phase input port

Abstract

In high speed large systems, global clocking is used to protect clocked I/O from data read failure due to clock skew. There are many drawbacks in global clock distribution utilized to reduce the clock skew. This paper addresses a self-tested self-synchronization (STSS) method implemented by a two-phase input port for parallel data transfer between blocks. A test signal is added to remove the data read failure. The advantages of this method are: very high data throughput; less power consumption in clock distribution; no constraints on clock skew and system scale; easy in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. By using a jitter injected test signal, robust parallel data transfer between blocks with arbitrary local clock phases is achieved and the problem of global synchronization is avoided in designing high performance ULSI.