六阶CMOS sigma-delta调制器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI:10.1109/ASIC.1998.722804

H. Y. San, S. M. Rezaul Hasan

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引用次数: 3

摘要

提出了一种六阶σ - δ调制器。通过四级级联降噪网络实现六阶噪声整形。行为仿真结果表明，级联的2-1-1-2(二阶-一阶-一阶-二阶)具有很强的鲁棒性，适合大规模集成电路的实现。利用MOSIS技术，采用2 /spl μ m CMOS工艺制作了实验样机。测量结果表明，该调制器在采样率为1.024 MHz，过采样比为16的情况下，在32 kHz带宽下实现了89 dB (14.8 bit)的峰值信噪比和92 dB (15.3 bit)的动态范围。调制器在+/- 3.3 V电源电压下耗散79 mW。

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A sixth-order CMOS sigma-delta modulator

A sixth-order sigma-delta modulator is presented. Sixth-order noise shaping is achieved though four stage cascaded noise cancellation network. Behavioral simulation shows that cascaded 2-1-1-2, (second order-first order-first order-second order) is very robust and suitable for VLSI implementation. An experimental prototype was fabricated using 2 /spl mu/m CMOS process by MOSIS. Measurement result shows that the modulator achieved 89 dB (14.8 bit) peak SNR and 92 dB (15.3 bit) dynamic range for 32 kHz bandwidth at a sampling rate of 1.024 MHz which corresponds to an oversampling ratio of 16. The modulator dissipates 79 mW at +/- 3.3 V supply voltage.

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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